From 17dd970d478bb6b68ebea4776a500b15b2b99cf6 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Tue, 2 Jul 2024 19:27:43 +0800
Subject: [PATCH] =?UTF-8?q?=E4=B8=8A=E4=BC=A0bugfix?=
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---
 src/main/scala/backBoard/SpiSlv.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/SpiSlv.scala b/src/main/scala/backBoard/SpiSlv.scala
index 7a19cb0..467d487 100644
--- a/src/main/scala/backBoard/SpiSlv.scala
+++ b/src/main/scala/backBoard/SpiSlv.scala
@@ -137,7 +137,7 @@ with BackBoardSpiSlv{
 
 
   io.lvdsSlv.upstream_tx_data_in :=
-    Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
+    Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
 
   val int = RegInit(false.B); interrupt := int
   when( int ){