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上传bugfix

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RuigeLee
2024-07-02 19:27:43 +08:00
parent bcbaa5b39b
commit 17dd970d47
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/backBoard/SpiSlv.scala
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@@ -137,7 +137,7 @@ with BackBoardSpiSlv{
io.lvdsSlv.upstream_tx_data_in := io.lvdsSlv.upstream_tx_data_in :=
Mux(upCnt === 0.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar) Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
val int = RegInit(false.B); interrupt := int val int = RegInit(false.B); interrupt := int
when( int ){ when( int ){