Merge branch 'feature/ebmmu' into feature/ShinTop
# Conflicts: # src/main/scala/backBoard/shin/SlaveParser.scala # src/main/scala/backBoard/shin/SlaveRecParser.scala # src/main/scala/backBoard/shin/SlaveSendGen.scala
This commit is contained in:
Ruige Lee
@@ -16,9 +16,15 @@ class SubMsgHeader extends Bundle{
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val address = UInt(16.W) //子报文地址
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val operator = UInt(4.W) //子报文命令类型
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val length = UInt(12.W) //子报文负载长度
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val workCnt = UInt(16.W) //子报文工作计数
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def isSeqIndex = style === 0.U
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def isLgcIndex = style === 2.U
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}
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class SubMsgTail extends Bundle{
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val workCnt = UInt(16.W) //子报文工作计数
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}
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// class ShareSRAMIO extends Bundle{
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@@ -65,6 +71,7 @@ class SlaveParserIO extends Bundle{
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val isLoop = Output(Bool())
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val cReg = Input(new CommonRegisterBundle)
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val sReg = Input(new SlaveRegisterBundle)
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val lvds = new RegAccessInterfaceIO
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@@ -75,6 +82,8 @@ class SlaveParserIO extends Bundle{
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abstract class SlaveParserBase extends Module{
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val io: SlaveParserIO = IO(new SlaveParserIO)
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val sReg = io.sReg
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val FRAME_STYLE_COMMON = 0.U
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@@ -91,11 +100,13 @@ abstract class SlaveParserBase extends Module{
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val STATE_IDLE = 0.U //空闲
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val STATE_HEADER = 1.U //包头
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val STATE_SUBMSG_HEADER = 2.U //子报文头
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val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
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val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
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val STATE_PAYLOAD_DATA = 3.U //子报文数据
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val STATE_CRC = 4.U //CRC校验
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val STATE_ERROR = 5.U //
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val STATE_SUBMSG_TAIL = 4.U
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val STATE_CRC = 5.U //CRC校验
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val STATE_ERROR = 6.U //
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val STATE_WAIT = 7.U
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@@ -108,9 +119,7 @@ abstract class SlaveParserBase extends Module{
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val isAckProbe = RegInit(false.B)
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val isLastDevice: Bool = RegInit(true.B)
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// val isDevOnLeft = RegInit(0.U(2.W)); io.isDevOnLeft := isDevOnLeft
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// val isDevOnLeftModify = RegInit(false.B); io.isDevOnLeftModify := isDevOnLeftModify
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// val indexOfLeftDev = RegInit(0.U(14.W)); io.indexOfLeftDev := indexOfLeftDev
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io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U )
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val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify
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val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev
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@@ -165,18 +174,21 @@ abstract class SlaveParserBase extends Module{
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////////////////////////////////////////
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//子报文
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val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isUpSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isDownSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isUpSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isDownSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isUpSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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//接收子报文
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val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
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val upSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
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val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
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val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
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val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头
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val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) }
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val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
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@@ -188,37 +200,42 @@ abstract class SlaveParserBase extends Module{
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//下行接收
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when( downRecParser.io.subMsgReq.fire ){
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when( downRecParser.io.subMsgHeadReq.fire ){
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when( isDownRecPing ){
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downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex
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downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style
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downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address
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downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator
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downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length
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downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt
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downSubMsgInfo(0).source := 0.U
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downSubMsgHeadInfo(0).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex
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downSubMsgHeadInfo(0).style := downRecParser.io.subMsgHeadReq.bits.style
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downSubMsgHeadInfo(0).address := downRecParser.io.subMsgHeadReq.bits.address
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downSubMsgHeadInfo(0).operator := downRecParser.io.subMsgHeadReq.bits.operator
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downSubMsgHeadInfo(0).length := downRecParser.io.subMsgHeadReq.bits.length
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downSubMsgHeadInfo(0).source := 0.U
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} .otherwise{ //pong
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downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex
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downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style
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downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address
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downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator
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downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length
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downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt
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downSubMsgInfo(1).source := 1.U
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downSubMsgHeadInfo(1).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex
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downSubMsgHeadInfo(1).style := downRecParser.io.subMsgHeadReq.bits.style
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downSubMsgHeadInfo(1).address := downRecParser.io.subMsgHeadReq.bits.address
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downSubMsgHeadInfo(1).operator := downRecParser.io.subMsgHeadReq.bits.operator
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downSubMsgHeadInfo(1).length := downRecParser.io.subMsgHeadReq.bits.length
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downSubMsgHeadInfo(1).source := 1.U
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}
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}
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when( downRecParser.io.subMsgTailReq.fire ){
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when( isDownRecPing ){
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downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt
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} .otherwise{ //pong
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downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt
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}
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}
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when( ~isDownRecPing ){ //req fire 后 已经反相
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when( isDownRecPing ){ //req fire 后
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downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
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downRecFifo(0).io.enq.bits := downRecParser.io.data.bits
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downRecParser.io.data.ready := downRecFifo(0).io.enq.ready
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downRecFifo(1).io.enq.valid := false.B
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downRecFifo(1).io.enq.bits := 0.U
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} .otherwise{
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downRecFifo(0).io.enq.valid := false.B
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downRecFifo(0).io.enq.bits := 0.U
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@@ -233,27 +250,31 @@ abstract class SlaveParserBase extends Module{
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//上行接收
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when( upRecParser.io.subMsgReq.fire ){
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when( upRecParser.io.subMsgHeadReq.fire ){
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when( isUpRecPing ){
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upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex
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upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style
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upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address
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upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator
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upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length
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upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt
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upSubMsgInfo(0).source := 0.U
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upSubMsgHeadInfo(0).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex
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upSubMsgHeadInfo(0).style := upRecParser.io.subMsgHeadReq.bits.style
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upSubMsgHeadInfo(0).address := upRecParser.io.subMsgHeadReq.bits.address
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upSubMsgHeadInfo(0).operator := upRecParser.io.subMsgHeadReq.bits.operator
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upSubMsgHeadInfo(0).length := upRecParser.io.subMsgHeadReq.bits.length
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upSubMsgHeadInfo(0).source := 0.U
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} .otherwise{
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upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex
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upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style
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upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address
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upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator
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upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length
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upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt
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upSubMsgInfo(1).source := 1.U
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upSubMsgHeadInfo(1).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex
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upSubMsgHeadInfo(1).style := upRecParser.io.subMsgHeadReq.bits.style
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upSubMsgHeadInfo(1).address := upRecParser.io.subMsgHeadReq.bits.address
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upSubMsgHeadInfo(1).operator := upRecParser.io.subMsgHeadReq.bits.operator
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upSubMsgHeadInfo(1).length := upRecParser.io.subMsgHeadReq.bits.length
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upSubMsgHeadInfo(1).source := 1.U
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}
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}
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when( upRecParser.io.subMsgTailReq.fire ){
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when( isUpRecPing ){
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upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt
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} .otherwise{
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upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt
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}
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}
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@@ -267,31 +288,59 @@ abstract class SlaveParserBase extends Module{
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downSendGen.io.subMsgReq.valid :=
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( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1))
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downSendGen.io.subMsgHeadReq.valid :=
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( isDownSendPing & isDownSubMsgHeadValid(0) ) | (~isDownSendPing & isDownSubMsgHeadValid(1))
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downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) )
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downSendGen.io.subMsgHeadReq.bits := Mux( isDownSendPing, downSubMsgHeadInfo(0), downSubMsgHeadInfo(1) )
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when( downSendGen.io.subMsgReq.fire ){ //ready
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isDownSendPing := ~isDownSendPing
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downSendGen.io.subMsgTailReq.valid :=
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( isDownSendPing & isDownSubMsgTailValid(0) ) | ( ~isDownSendPing & isDownSubMsgTailValid(1))
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downSendGen.io.subMsgTailReq.bits := Mux( isDownSendPing, downSubMsgTailInfo(0), downSubMsgTailInfo(1) )
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when( downSendGen.io.subMsgHeadReq.fire ){ //ready
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when( isDownSendPing ){
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assert( isDownSubMsgValid(0) )
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isDownSubMsgValid(0) := false.B
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assert( isDownSubMsgHeadValid(0) )
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isDownSubMsgHeadValid(0) := false.B
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} .otherwise{
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assert( isDownSubMsgValid(1) )
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isDownSubMsgValid(1) := false.B
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assert( isDownSubMsgHeadValid(1) )
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isDownSubMsgHeadValid(1) := false.B
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}
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} .elsewhen( downRecParser.io.subMsgReq.fire ){
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isDownRecPing := ~isDownRecPing
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} .elsewhen( downRecParser.io.subMsgHeadReq.fire ){
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when( isDownRecPing ){
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assert( ~isDownSubMsgValid(0) )
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isDownSubMsgValid(0) := true.B
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assert( ~isDownSubMsgHeadValid(0) )
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isDownSubMsgHeadValid(0) := true.B
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} .otherwise{
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assert( ~isDownSubMsgValid(1) )
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isDownSubMsgValid(1) := true.B
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assert( ~isDownSubMsgHeadValid(1) )
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isDownSubMsgHeadValid(1) := true.B
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}
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}
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when( downSendGen.io.subMsgTailReq.fire ){
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when( isDownSendPing ){
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assert( isDownSubMsgTailValid(0) )
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isDownSubMsgTailValid(0) := false.B
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} .otherwise{
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assert( isDownSubMsgTailValid(1) )
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isDownSubMsgTailValid(1) := false.B
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}
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} .elsewhen( downRecParser.io.subMsgTailReq.fire ){
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when( isDownRecPing ){
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assert( ~isDownSubMsgTailValid(0) )
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isDownSubMsgTailValid(0) := true.B
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} .otherwise{
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assert( ~isDownSubMsgTailValid(1) )
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isDownSubMsgTailValid(1) := true.B
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}
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}
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when( downSendGen.io.subMsgTailReq.fire ){ //ready
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isDownSendPing := ~isDownSendPing
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} .elsewhen( downRecParser.io.subMsgTailReq.fire ){
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isDownRecPing := ~isDownRecPing
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}
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downRecFifo(0).io.deq <> downSendGen.io.data(0)
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downRecFifo(1).io.deq <> downSendGen.io.data(1)
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@@ -300,32 +349,61 @@ abstract class SlaveParserBase extends Module{
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//子报文上行发送
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upSendGen.io.subMsgReq.valid :=
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( isUpSendPing & isUpSubMsgValid(0) ) |
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( ~isUpSendPing & isUpSubMsgValid(1) )
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upSendGen.io.subMsgHeadReq.valid :=
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( isUpSendPing & isUpSubMsgHeadValid(0) ) |
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( ~isUpSendPing & isUpSubMsgHeadValid(1) )
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upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) )
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upSendGen.io.subMsgHeadReq.bits := Mux( isUpSendPing, upSubMsgHeadInfo(0), upSubMsgHeadInfo(1) )
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when( upSendGen.io.subMsgReq.fire ){ //ready
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isUpSendPing := ~isUpSendPing
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upSendGen.io.subMsgTailReq.valid :=
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( isUpSendPing & isUpSubMsgTailValid(0) ) |
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( ~isUpSendPing & isUpSubMsgTailValid(1) )
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upSendGen.io.subMsgTailReq.bits := Mux( isUpSendPing, upSubMsgTailInfo(0), upSubMsgTailInfo(1) )
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when( upSendGen.io.subMsgHeadReq.fire ){ //ready
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when( isUpSendPing ){
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assert( isUpSubMsgValid(0) )
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isUpSubMsgValid(0) := false.B
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assert( isUpSubMsgHeadValid(0) )
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isUpSubMsgHeadValid(0) := false.B
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} .otherwise{
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assert( isUpSubMsgValid(1) )
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isUpSubMsgValid(1) := false.B
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assert( isUpSubMsgHeadValid(1) )
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isUpSubMsgHeadValid(1) := false.B
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}
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}.elsewhen( upRecParser.io.subMsgReq.fire ){
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isUpRecPing := ~isUpRecPing
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}.elsewhen( upRecParser.io.subMsgHeadReq.fire ){
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when( isUpRecPing ){
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assert( ~isUpSubMsgValid(0) )
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isUpSubMsgValid(0) := true.B
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assert( ~isUpSubMsgHeadValid(0) )
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isUpSubMsgHeadValid(0) := true.B
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} .otherwise{
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assert( ~isUpSubMsgValid(1) )
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isUpSubMsgValid(1) := true.B
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assert( ~isUpSubMsgHeadValid(1) )
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isUpSubMsgHeadValid(1) := true.B
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}
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}
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when( upSendGen.io.subMsgTailReq.fire ){
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when( isUpSendPing ){
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assert( isUpSubMsgTailValid(0) )
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isUpSubMsgTailValid(0) := false.B
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} .otherwise{
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assert( isUpSubMsgTailValid(1) )
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isUpSubMsgTailValid(1) := false.B
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}
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} .elsewhen( upRecParser.io.subMsgTailReq.fire ){
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when( isUpRecPing ){
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assert( ~isUpSubMsgTailValid(0) )
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isUpSubMsgTailValid(0) := true.B
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} .otherwise{
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assert( ~isUpSubMsgTailValid(1) )
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isUpSubMsgTailValid(1) := true.B
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}
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}
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when( upSendGen.io.subMsgTailReq.fire ){ //ready
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isUpSendPing := ~isUpSendPing
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}.elsewhen( upRecParser.io.subMsgTailReq.fire ){
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isUpRecPing := ~isUpRecPing
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}
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upRecFifo(0).io.deq <> upSendGen.io.data(0)
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upRecFifo(1).io.deq <> upSendGen.io.data(1)
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@@ -346,22 +424,40 @@ abstract class SlaveParserBase extends Module{
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trait SlaveParserIndex{ this: SlaveParserBase =>
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//下行接收
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when( downRecParser.io.subMsgReq.fire &
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downRecParser.io.subMsgReq.bits.devIndex === 0.U &
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downRecParser.io.subMsgReq.bits.style === 0.U &
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downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址
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localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
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indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U)
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when( isDownRecPing ){
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downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
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} .otherwise{ //pong
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downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
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//下行接收
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when( downRecParser.io.subMsgTailReq.fire ){
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when( isDownRecPing &
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downSubMsgHeadInfo(0).devIndex === 0.U &
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downSubMsgHeadInfo(0).style === 0.U &
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downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_INDEX
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||||
){
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localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U)
|
||||
downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
} .elsewhen( ~isDownRecPing &
|
||||
downSubMsgHeadInfo(1).devIndex === 0.U &
|
||||
downSubMsgHeadInfo(1).style === 0.U &
|
||||
downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_INDEX
|
||||
){ //pong
|
||||
localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U)
|
||||
downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//上行接收 获取右侧索引号
|
||||
// when( downRecParser.io.subMsgHeadReq.fire &
|
||||
// downRecParser.io.subMsgHeadReq.bits.devIndex === 0.U &
|
||||
// downRecParser.io.subMsgHeadReq.bits.style === 0.U &
|
||||
// downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址
|
||||
// localDevIndex := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
|
||||
// indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgHeadReq.bits.workCnt + 2.U)
|
||||
// when( isDownRecPing ){
|
||||
// downSubMsgHeadInfo(0).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
|
||||
// } .otherwise{ //pong
|
||||
// downSubMsgHeadInfo(1).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U
|
||||
// }
|
||||
// }
|
||||
|
||||
}
|
||||
|
||||
@@ -371,24 +467,27 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
|
||||
|
||||
trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
|
||||
val isDownLgcWorked = RegInit(false.B)
|
||||
val isUpLgcWorked = RegInit(false.B)
|
||||
|
||||
//下行接收
|
||||
when( downRecParser.io.subMsgReq.fire ){
|
||||
when( downRecParser.io.subMsgTailReq.fire ){
|
||||
when( isDownRecPing ){
|
||||
//override
|
||||
when(
|
||||
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
|
||||
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & isDownLgcWorked ) ) ) |
|
||||
( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
) { //自身包//写操作或读写操作)
|
||||
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
|
||||
downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
}
|
||||
|
||||
} .otherwise{ //pong
|
||||
//override
|
||||
when(
|
||||
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE ) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
|
||||
( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE ) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & isDownLgcWorked ) ) ) |
|
||||
( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
) { //自身包//写操作或读写操作 )
|
||||
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
|
||||
downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -398,32 +497,93 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
//写入 SM或寄存器空间
|
||||
|
||||
val addrw = Reg(UInt(15.W))
|
||||
val logicAddrwNext = Wire( UInt(30.W) )
|
||||
val logicAddrw = RegNext(logicAddrwNext)
|
||||
|
||||
val isWRReg = (addrw(14,11) === "b0000".U)
|
||||
val isWRSM0 = (addrw(14,11) === "b0001".U)
|
||||
val isWRSM2 = (addrw(14,11) === "b0011".U)
|
||||
val isWRSM4 = (addrw(14,11) === "b0101".U)
|
||||
val isWRSM6 = (addrw(14,11) === "b0111".U)
|
||||
val isWRSM0 = (addrw(14,11) === "b0001".U)
|
||||
val isWRSM2 = (addrw(14,11) === "b0011".U)
|
||||
val isWRSM4 = (addrw(14,11) === "b0101".U)
|
||||
val isWRSM6 = (addrw(14,11) === "b0111".U)
|
||||
|
||||
val downTransLenCnt = RegInit(0.U)
|
||||
|
||||
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
|
||||
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(0).devIndex === localDevIndex)) |
|
||||
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(1).devIndex === localDevIndex)) |
|
||||
( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) |
|
||||
( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
|
||||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
|
||||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) |
|
||||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
)
|
||||
|
||||
when( downRecParser.io.subMsgReq.fire & (
|
||||
downRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
|
||||
downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE |
|
||||
downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
|
||||
)
|
||||
){
|
||||
addrw := downRecParser.io.subMsgReq.bits.address
|
||||
} .elsewhen( isWrite & downRecParser.io.data.fire ){
|
||||
addrw := addrw + 1.U
|
||||
|
||||
val isDownLgcAddrwAcquireTrans = //是否触发地址转换
|
||||
(downTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
|
||||
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)
|
||||
}.reduce(_|_))
|
||||
|
||||
val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).pAddr
|
||||
}
|
||||
)
|
||||
|
||||
val acquireDownTransLen = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).length
|
||||
}
|
||||
)
|
||||
|
||||
when( isDownLgcAddrwAcquireTrans ){ //装填计数器
|
||||
downTransLenCnt := acquireDownTransLen
|
||||
} .elsewhen( downRecParser.io.data.fire & downTransLenCnt =/= 0.U){
|
||||
downTransLenCnt := downTransLenCnt - 1.U
|
||||
}
|
||||
|
||||
when( downRecParser.io.subMsgTailReq.fire ){
|
||||
isDownLgcWorked := false.B
|
||||
} .elsewhen( isDownLgcAddrwAcquireTrans ){
|
||||
isDownLgcWorked := true.B
|
||||
}
|
||||
|
||||
//组合逻辑
|
||||
when( downRecParser.io.subMsgHeadReq.fire & (
|
||||
(downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex
|
||||
)){//组合逻辑
|
||||
logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address )
|
||||
} .elsewhen( downRecParser.io.data.fire & (
|
||||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
|
||||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
|
||||
)){//组合逻辑
|
||||
logicAddrwNext := logicAddrw + 1.U
|
||||
} .otherwise{//组合逻辑
|
||||
logicAddrwNext := logicAddrw
|
||||
}
|
||||
|
||||
when(
|
||||
( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) |
|
||||
( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
|
||||
){ //常规寻址
|
||||
when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填
|
||||
addrw := downRecParser.io.subMsgHeadReq.bits.address
|
||||
} .elsewhen( isWrite & downRecParser.io.data.fire ){
|
||||
addrw := addrw + 1.U
|
||||
}
|
||||
} .elsewhen( isDownLgcAddrwAcquireTrans & (
|
||||
( downRecParser.io.subMsgHeadReq.fire & (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ) |
|
||||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
|
||||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
|
||||
)){
|
||||
addrw := acquireDownPhyAddrw
|
||||
} .elsewhen(
|
||||
isWrite & downRecParser.io.data.fire & (
|
||||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
|
||||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
|
||||
) ){
|
||||
assert(~isDownLgcAddrwAcquireTrans)
|
||||
addrw := Mux( downTransLenCnt === 0.U, 0.U, addrw + 1.U )
|
||||
}
|
||||
|
||||
io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire
|
||||
io.lvds.dataw := downRecParser.io.data.bits
|
||||
@@ -445,31 +605,26 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
io.sram_w(3).dataw := downRecParser.io.data.bits
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// val SUBMSG_OPERATOR_BOARDREAD = "hd".U
|
||||
// val SUBMSG_OPERATOR_BOARDWRITE = "he".U
|
||||
// val SUBMSG_OPERATOR_BOARDRDWR = "hf".U
|
||||
|
||||
|
||||
//上行接收
|
||||
when( upRecParser.io.subMsgReq.fire ){
|
||||
when( upRecParser.io.subMsgTailReq.fire ){
|
||||
when( isUpRecPing ){
|
||||
//override
|
||||
when(
|
||||
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
|
||||
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||||
( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
){ //自身包//读或读写
|
||||
upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
|
||||
upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
}
|
||||
} .otherwise{
|
||||
//override
|
||||
when(
|
||||
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
|
||||
( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||||
( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
){ //自身包//读或读写 )
|
||||
upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U
|
||||
upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -478,18 +633,67 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
|
||||
|
||||
|
||||
val upTransLenCnt = RegInit(0.U)
|
||||
|
||||
//读出uSM
|
||||
val isRead =
|
||||
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
|
||||
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex) |
|
||||
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex) |
|
||||
(~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
|
||||
( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
|
||||
)
|
||||
)
|
||||
|
||||
val addrr = Reg(UInt(15.W))
|
||||
val logicAddrrNext = Wire( UInt(30.W) )
|
||||
val logicAddrr = RegNext(logicAddrrNext)
|
||||
|
||||
|
||||
val isUpLgcAddrrAcquireTrans = //是否触发地址转换
|
||||
(upTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
|
||||
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)
|
||||
}.reduce(_|_))
|
||||
|
||||
val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).pAddr
|
||||
}
|
||||
)
|
||||
|
||||
val acquireUpTransLen = Mux1H( //选择一个ebmmu
|
||||
(0 until 8).map{ i =>
|
||||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
|
||||
sReg.ebmmu(i).length
|
||||
}
|
||||
)
|
||||
|
||||
when( isUpLgcAddrrAcquireTrans & (
|
||||
(upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
|
||||
)){ //装填计数器
|
||||
upTransLenCnt := acquireUpTransLen
|
||||
} .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){
|
||||
upTransLenCnt := upTransLenCnt - 1.U
|
||||
}
|
||||
|
||||
when( upRecParser.io.subMsgTailReq.fire ){
|
||||
isUpLgcWorked := false.B
|
||||
} .elsewhen( isUpLgcAddrrAcquireTrans ){
|
||||
isUpLgcWorked := true.B
|
||||
}
|
||||
|
||||
//组合逻辑
|
||||
when( upRecParser.io.subMsgHeadReq.fire & (
|
||||
(upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex
|
||||
)){//组合逻辑
|
||||
logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address )
|
||||
} .elsewhen( upRecParser.io.data.fire){
|
||||
when(
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex )
|
||||
){//组合逻辑
|
||||
logicAddrrNext := logicAddrr + 1.U
|
||||
} .otherwise{
|
||||
logicAddrrNext := 0.U
|
||||
}
|
||||
} .otherwise{//组合逻辑
|
||||
logicAddrrNext := logicAddrr
|
||||
}
|
||||
|
||||
|
||||
val isRDReg = addrr(14,11) === "b0000".U
|
||||
val isRDSM1 = addrr(14,11) === "b0010".U
|
||||
@@ -497,35 +701,66 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
val isRDSM5 = addrr(14,11) === "b0110".U
|
||||
val isRDSM7 = addrr(14,11) === "b1000".U
|
||||
|
||||
val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) |
|
||||
upRecParser.io.data.fire )
|
||||
|
||||
when( upRecParser.io.subMsgReq.fire & (
|
||||
upRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
|
||||
upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD |
|
||||
upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
|
||||
val isSeqRead =
|
||||
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) |
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
|
||||
)
|
||||
) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
|
||||
|
||||
val isLgcRead =
|
||||
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
|
||||
)
|
||||
) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
|
||||
|
||||
val isLvdsEnR = isSeqRead | isLgcRead
|
||||
|
||||
|
||||
|
||||
when(
|
||||
((upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgHeadReq.bits.isSeqIndex & upRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex)) |
|
||||
( upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
|
||||
){
|
||||
addrr := upRecParser.io.subMsgReq.bits.address
|
||||
} .elsewhen( isLvdsEnR ){
|
||||
addrr := addrr + 1.U
|
||||
when( upRecParser.io.subMsgHeadReq.fire){
|
||||
addrr := upRecParser.io.subMsgHeadReq.bits.address
|
||||
} .elsewhen(isLvdsEnR){
|
||||
addrr := addrr + 1.U
|
||||
}
|
||||
} .elsewhen( isUpLgcAddrrAcquireTrans & (
|
||||
(upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
|
||||
)){
|
||||
addrr := acquireUpPhyAddrr
|
||||
} .elsewhen( isLvdsEnR & (
|
||||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
|
||||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
|
||||
)){
|
||||
assert(~isUpLgcAddrrAcquireTrans)
|
||||
addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
|
||||
}
|
||||
|
||||
|
||||
|
||||
val upStreamData = Mux1H(Seq(
|
||||
isRDReg -> io.lvds.datar,
|
||||
isRDSM1 -> io.sram_r(0).datar,
|
||||
isRDSM3 -> io.sram_r(1).datar,
|
||||
isRDSM5 -> io.sram_r(2).datar,
|
||||
isRDSM7 -> io.sram_r(3).datar,
|
||||
isRDReg -> io.lvds.datar,
|
||||
isRDSM1 -> io.sram_r(0).datar,
|
||||
isRDSM3 -> io.sram_r(1).datar,
|
||||
isRDSM5 -> io.sram_r(2).datar,
|
||||
isRDSM7 -> io.sram_r(3).datar,
|
||||
))
|
||||
|
||||
|
||||
when( ~isUpRecPing ){ //req fire 后 已经反相
|
||||
when( isUpRecPing ){
|
||||
upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
|
||||
upRecFifo(0).io.enq.bits :=
|
||||
Mux(
|
||||
( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex, upStreamData,
|
||||
Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
|
||||
( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) | (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
|
||||
Mux( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
|
||||
upRecParser.io.data.bits )
|
||||
)
|
||||
upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
|
||||
@@ -539,8 +774,8 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
|
||||
upRecFifo(1).io.enq.bits :=
|
||||
Mux(
|
||||
( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex, upStreamData,
|
||||
Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
|
||||
( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) | (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
|
||||
Mux( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
|
||||
upRecParser.io.data.bits
|
||||
)
|
||||
)
|
||||
@@ -588,18 +823,40 @@ trait SlaveParserRW{ this: SlaveParserBase =>
|
||||
|
||||
|
||||
trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
|
||||
// when( upRecParser.io.subMsgTailReq.fire ){
|
||||
// when( isUpRecPing ){
|
||||
// //override
|
||||
// when(
|
||||
// ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||||
// ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
// ){ //自身包//读或读写
|
||||
// upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
// }
|
||||
// } .otherwise{
|
||||
// //override
|
||||
// when(
|
||||
// ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||||
// ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||||
// ){ //自身包//读或读写 )
|
||||
// upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
|
||||
|
||||
//下行接收
|
||||
when( downRecParser.io.subMsgReq.fire ){
|
||||
when( downRecParser.io.subMsgTailReq.fire ){
|
||||
when( isDownRecPing ){
|
||||
//override
|
||||
when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包
|
||||
downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
|
||||
when( downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) { //同步包
|
||||
downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
}
|
||||
|
||||
} .otherwise{ //pong
|
||||
//override
|
||||
when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包 )
|
||||
downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
|
||||
when( downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 )
|
||||
downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -640,8 +897,8 @@ trait SlaveParserSync{ this: SlaveParserBase =>
|
||||
|
||||
//下行接收
|
||||
val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
|
||||
( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === SUBMSG_OPERATOR_SYNC ) |
|
||||
( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === SUBMSG_OPERATOR_SYNC )
|
||||
( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) |
|
||||
( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
|
||||
)
|
||||
|
||||
val syncCnt = Reg(UInt(4.W))
|
||||
|
||||
Reference in New Issue
Block a user