diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index fb034aa..bdbe97e 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -3,6 +3,19 @@ package BACK import chisel3._ import chisel3.util._ + +class EBMMU_Bundle extends Bundle{ + val lAddr = UInt(30.W) + val pAddr = UInt(16.W) + val length = UInt(16.W) + val op = UInt(8.W) + val isEnable = Bool() + + def EBMMU_OP_RD = op === 1.U + def EBMMU_OP_WR = op === 2.U + def EBMMU_OP_RW = op === 3.U +} + class CommonRegisterBundle extends Bundle{ val mstOrSlv = UInt(2.W) def modeSel:Bool = mstOrSlv === "h1".U @@ -72,13 +85,7 @@ class SlaveRegisterBundle extends Bundle{ // val nodeSetAddr = UInt(16.W) - // val ebmmu = Vec(8, new Bundle{ - // val logicAddr = UInt(32.W) - // val length = UInt(16.W) - // val phyAddr = UInt(32.W) - // val op = UInt(2.W) - // val enable = Bool() - // }) + val ebmmu = Vec(8, new EBMMU_Bundle) // val intStatus = UInt(16.W) // val mb = Vec(8, new Bundle{ @@ -364,6 +371,21 @@ abstract class InterfaceBase extends Module{ ( 0 until 128 ).map{ i => ( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i) } ++ + ( 0 until 8 ).map{ i => Seq( + ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0), + ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8), + ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16), + ( ( addr === ( "h203".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(29,24), + + ( ( addr === ( "h204".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr( 7, 0), + ( ( addr === ( "h205".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr(15, 8), + + ( ( addr === ( "h206".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length( 7, 0), + ( ( addr === ( "h207".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length(15, 8), + + ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op, + ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable, + )}.reduce(_++_) ++ ( 0 until 8 ).map{ i => ( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0) } ++ @@ -566,19 +588,19 @@ trait InterfaceMCUop{ this: InterfaceBase => for( i <- 0 until 8 ){ when( isEnW & addrw === "h400".U & dataw.extract(i) ){ wdtStatus(i) := false.B - } .elsewhen(io.wdtTrigger(i)){ + } .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){ wdtStatus(i) := true.B } when( isEnW & addrw === "h401".U & dataw.extract(i) ){ wdtStatus(8+i) := false.B - } .elsewhen(io.wdtTrigger(8+i)){ + } .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){ wdtStatus(8+i) := true.B } } for( i <- 0 until 1 ){ when( isEnW & addrw === "h402".U & dataw.extract(i) ){ wdtStatus(16+i) := false.B - } .elsewhen(io.wdtTrigger(16+i)){ + } .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){ wdtStatus(16+i) := true.B } } @@ -725,6 +747,33 @@ trait InterfaceLVDSop{ this: InterfaceBase => } } } + + + ( 0 until 8 ).map{ i => + sReg.ebmmu(i).lAddr := Cat( + RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ), + ) + + sReg.ebmmu(i).pAddr := Cat( + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ), + ) + + sReg.ebmmu(i).length := Cat( + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ), + ) + + sReg.ebmmu(i).op := + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) + + sReg.ebmmu(i).isEnable := + RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) ) + } + } trait InterfaceSync{ this: InterfaceBase => diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala index befeb8e..dd51fcb 100644 --- a/src/main/scala/backBoard/shin/SMUnit.scala +++ b/src/main/scala/backBoard/shin/SMUnit.scala @@ -48,14 +48,14 @@ abstract class SMUnitBase(depth: Int = 4) extends Module { val isEmpty = ( wPtr === rPtr ) - when( io.enq ){ + when( io.enq & ~isFull ){ wPtr := wPtr + 1.U - assert( ~isFull) + // assert( ~isFull) } - when( io.deq ){ + when( io.deq & ~isEmpty ){ rPtr := rPtr + 1.U - assert( ~isEmpty ) + // assert( ~isEmpty ) } for( i <- 0 until depth ){ diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 8796ce8..9f210f0 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -329,6 +329,7 @@ trait ShinTopSlave{ this: ShinTopBase => } slaveParser.io.cReg := interface.io.cReg + slaveParser.io.sReg := interface.io.sReg when( interface.io.cReg.modeSel === false.B ){ @@ -370,8 +371,8 @@ trait ShinTopSlave{ this: ShinTopBase => } - slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) - slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) + slaveParser.io.intHWClr(0) := interface.io.intHWClr(0) + slaveParser.io.intHWClr(1) := interface.io.intHWClr(1) interface.io.lvds <> slaveParser.io.lvds diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 6478673..07768d4 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -16,9 +16,15 @@ class SubMsgHeader extends Bundle{ val address = UInt(16.W) //子报文地址 val operator = UInt(4.W) //子报文命令类型 val length = UInt(12.W) //子报文负载长度 - val workCnt = UInt(16.W) //子报文工作计数 + + + def isSeqIndex = style === 0.U + def isLgcIndex = style === 2.U } +class SubMsgTail extends Bundle{ + val workCnt = UInt(16.W) //子报文工作计数 +} // class ShareSRAMIO extends Bundle{ @@ -65,6 +71,7 @@ class SlaveParserIO extends Bundle{ val isLoop = Output(Bool()) val cReg = Input(new CommonRegisterBundle) + val sReg = Input(new SlaveRegisterBundle) val lvds = new RegAccessInterfaceIO @@ -75,6 +82,8 @@ class SlaveParserIO extends Bundle{ abstract class SlaveParserBase extends Module{ val io: SlaveParserIO = IO(new SlaveParserIO) + val sReg = io.sReg + val FRAME_STYLE_COMMON = 0.U @@ -91,11 +100,13 @@ abstract class SlaveParserBase extends Module{ val STATE_IDLE = 0.U //空闲 - val STATE_HEADER = 1.U //包头 - val STATE_SUBMSG_HEADER = 2.U //子报文头 + val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 + val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型 val STATE_PAYLOAD_DATA = 3.U //子报文数据 - val STATE_CRC = 4.U //CRC校验 - val STATE_ERROR = 5.U // + val STATE_SUBMSG_TAIL = 4.U + val STATE_CRC = 5.U //CRC校验 + val STATE_ERROR = 6.U // + val STATE_WAIT = 7.U @@ -108,9 +119,7 @@ abstract class SlaveParserBase extends Module{ val isAckProbe = RegInit(false.B) val isLastDevice: Bool = RegInit(true.B) - // val isDevOnLeft = RegInit(0.U(2.W)); io.isDevOnLeft := isDevOnLeft - // val isDevOnLeftModify = RegInit(false.B); io.isDevOnLeftModify := isDevOnLeftModify - // val indexOfLeftDev = RegInit(0.U(14.W)); io.indexOfLeftDev := indexOfLeftDev + io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U ) val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev @@ -165,18 +174,21 @@ abstract class SlaveParserBase extends Module{ //////////////////////////////////////// //子报文 - val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } - val isUpSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } - + val isDownSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } + val isUpSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } + val isDownSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } + val isUpSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } //接收子报文 - val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头 - val upSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } + val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头 + val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } + val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头 + val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载 @@ -188,37 +200,42 @@ abstract class SlaveParserBase extends Module{ //下行接收 - when( downRecParser.io.subMsgReq.fire ){ + when( downRecParser.io.subMsgHeadReq.fire ){ when( isDownRecPing ){ - downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex - downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style - downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address - downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator - downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt - downSubMsgInfo(0).source := 0.U + downSubMsgHeadInfo(0).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex + downSubMsgHeadInfo(0).style := downRecParser.io.subMsgHeadReq.bits.style + downSubMsgHeadInfo(0).address := downRecParser.io.subMsgHeadReq.bits.address + downSubMsgHeadInfo(0).operator := downRecParser.io.subMsgHeadReq.bits.operator + downSubMsgHeadInfo(0).length := downRecParser.io.subMsgHeadReq.bits.length + downSubMsgHeadInfo(0).source := 0.U } .otherwise{ //pong - downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex - downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style - downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address - downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator - downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt - downSubMsgInfo(1).source := 1.U + downSubMsgHeadInfo(1).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex + downSubMsgHeadInfo(1).style := downRecParser.io.subMsgHeadReq.bits.style + downSubMsgHeadInfo(1).address := downRecParser.io.subMsgHeadReq.bits.address + downSubMsgHeadInfo(1).operator := downRecParser.io.subMsgHeadReq.bits.operator + downSubMsgHeadInfo(1).length := downRecParser.io.subMsgHeadReq.bits.length + downSubMsgHeadInfo(1).source := 1.U + } + } + + when( downRecParser.io.subMsgTailReq.fire ){ + when( isDownRecPing ){ + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + } .otherwise{ //pong + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt } } - when( ~isDownRecPing ){ //req fire 后 已经反相 + when( isDownRecPing ){ //req fire 后 downRecFifo(0).io.enq.valid := downRecParser.io.data.valid downRecFifo(0).io.enq.bits := downRecParser.io.data.bits downRecParser.io.data.ready := downRecFifo(0).io.enq.ready downRecFifo(1).io.enq.valid := false.B downRecFifo(1).io.enq.bits := 0.U - } .otherwise{ downRecFifo(0).io.enq.valid := false.B downRecFifo(0).io.enq.bits := 0.U @@ -233,27 +250,31 @@ abstract class SlaveParserBase extends Module{ //上行接收 - when( upRecParser.io.subMsgReq.fire ){ + when( upRecParser.io.subMsgHeadReq.fire ){ when( isUpRecPing ){ - upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex - upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style - upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address - upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator - upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length - upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt - upSubMsgInfo(0).source := 0.U + upSubMsgHeadInfo(0).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex + upSubMsgHeadInfo(0).style := upRecParser.io.subMsgHeadReq.bits.style + upSubMsgHeadInfo(0).address := upRecParser.io.subMsgHeadReq.bits.address + upSubMsgHeadInfo(0).operator := upRecParser.io.subMsgHeadReq.bits.operator + upSubMsgHeadInfo(0).length := upRecParser.io.subMsgHeadReq.bits.length + upSubMsgHeadInfo(0).source := 0.U } .otherwise{ - upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex - upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style - upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address - upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator - upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length - upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt - upSubMsgInfo(1).source := 1.U + upSubMsgHeadInfo(1).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex + upSubMsgHeadInfo(1).style := upRecParser.io.subMsgHeadReq.bits.style + upSubMsgHeadInfo(1).address := upRecParser.io.subMsgHeadReq.bits.address + upSubMsgHeadInfo(1).operator := upRecParser.io.subMsgHeadReq.bits.operator + upSubMsgHeadInfo(1).length := upRecParser.io.subMsgHeadReq.bits.length + upSubMsgHeadInfo(1).source := 1.U } } - + when( upRecParser.io.subMsgTailReq.fire ){ + when( isUpRecPing ){ + upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + } .otherwise{ + upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + } + } @@ -267,31 +288,59 @@ abstract class SlaveParserBase extends Module{ - downSendGen.io.subMsgReq.valid := - ( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1)) + downSendGen.io.subMsgHeadReq.valid := + ( isDownSendPing & isDownSubMsgHeadValid(0) ) | (~isDownSendPing & isDownSubMsgHeadValid(1)) - downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) ) + downSendGen.io.subMsgHeadReq.bits := Mux( isDownSendPing, downSubMsgHeadInfo(0), downSubMsgHeadInfo(1) ) - when( downSendGen.io.subMsgReq.fire ){ //ready - isDownSendPing := ~isDownSendPing + downSendGen.io.subMsgTailReq.valid := + ( isDownSendPing & isDownSubMsgTailValid(0) ) | ( ~isDownSendPing & isDownSubMsgTailValid(1)) + + downSendGen.io.subMsgTailReq.bits := Mux( isDownSendPing, downSubMsgTailInfo(0), downSubMsgTailInfo(1) ) + + + + when( downSendGen.io.subMsgHeadReq.fire ){ //ready when( isDownSendPing ){ - assert( isDownSubMsgValid(0) ) - isDownSubMsgValid(0) := false.B + assert( isDownSubMsgHeadValid(0) ) + isDownSubMsgHeadValid(0) := false.B } .otherwise{ - assert( isDownSubMsgValid(1) ) - isDownSubMsgValid(1) := false.B + assert( isDownSubMsgHeadValid(1) ) + isDownSubMsgHeadValid(1) := false.B } - } .elsewhen( downRecParser.io.subMsgReq.fire ){ - isDownRecPing := ~isDownRecPing + } .elsewhen( downRecParser.io.subMsgHeadReq.fire ){ when( isDownRecPing ){ - assert( ~isDownSubMsgValid(0) ) - isDownSubMsgValid(0) := true.B + assert( ~isDownSubMsgHeadValid(0) ) + isDownSubMsgHeadValid(0) := true.B } .otherwise{ - assert( ~isDownSubMsgValid(1) ) - isDownSubMsgValid(1) := true.B + assert( ~isDownSubMsgHeadValid(1) ) + isDownSubMsgHeadValid(1) := true.B } } + when( downSendGen.io.subMsgTailReq.fire ){ + when( isDownSendPing ){ + assert( isDownSubMsgTailValid(0) ) + isDownSubMsgTailValid(0) := false.B + } .otherwise{ + assert( isDownSubMsgTailValid(1) ) + isDownSubMsgTailValid(1) := false.B + } + } .elsewhen( downRecParser.io.subMsgTailReq.fire ){ + when( isDownRecPing ){ + assert( ~isDownSubMsgTailValid(0) ) + isDownSubMsgTailValid(0) := true.B + } .otherwise{ + assert( ~isDownSubMsgTailValid(1) ) + isDownSubMsgTailValid(1) := true.B + } + } + + when( downSendGen.io.subMsgTailReq.fire ){ //ready + isDownSendPing := ~isDownSendPing + } .elsewhen( downRecParser.io.subMsgTailReq.fire ){ + isDownRecPing := ~isDownRecPing + } downRecFifo(0).io.deq <> downSendGen.io.data(0) downRecFifo(1).io.deq <> downSendGen.io.data(1) @@ -300,32 +349,61 @@ abstract class SlaveParserBase extends Module{ //子报文上行发送 - upSendGen.io.subMsgReq.valid := - ( isUpSendPing & isUpSubMsgValid(0) ) | - ( ~isUpSendPing & isUpSubMsgValid(1) ) + upSendGen.io.subMsgHeadReq.valid := + ( isUpSendPing & isUpSubMsgHeadValid(0) ) | + ( ~isUpSendPing & isUpSubMsgHeadValid(1) ) - upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) ) + upSendGen.io.subMsgHeadReq.bits := Mux( isUpSendPing, upSubMsgHeadInfo(0), upSubMsgHeadInfo(1) ) - when( upSendGen.io.subMsgReq.fire ){ //ready - isUpSendPing := ~isUpSendPing + upSendGen.io.subMsgTailReq.valid := + ( isUpSendPing & isUpSubMsgTailValid(0) ) | + ( ~isUpSendPing & isUpSubMsgTailValid(1) ) + + upSendGen.io.subMsgTailReq.bits := Mux( isUpSendPing, upSubMsgTailInfo(0), upSubMsgTailInfo(1) ) + + when( upSendGen.io.subMsgHeadReq.fire ){ //ready when( isUpSendPing ){ - assert( isUpSubMsgValid(0) ) - isUpSubMsgValid(0) := false.B + assert( isUpSubMsgHeadValid(0) ) + isUpSubMsgHeadValid(0) := false.B } .otherwise{ - assert( isUpSubMsgValid(1) ) - isUpSubMsgValid(1) := false.B + assert( isUpSubMsgHeadValid(1) ) + isUpSubMsgHeadValid(1) := false.B } - }.elsewhen( upRecParser.io.subMsgReq.fire ){ - isUpRecPing := ~isUpRecPing + }.elsewhen( upRecParser.io.subMsgHeadReq.fire ){ when( isUpRecPing ){ - assert( ~isUpSubMsgValid(0) ) - isUpSubMsgValid(0) := true.B + assert( ~isUpSubMsgHeadValid(0) ) + isUpSubMsgHeadValid(0) := true.B } .otherwise{ - assert( ~isUpSubMsgValid(1) ) - isUpSubMsgValid(1) := true.B + assert( ~isUpSubMsgHeadValid(1) ) + isUpSubMsgHeadValid(1) := true.B } } + when( upSendGen.io.subMsgTailReq.fire ){ + when( isUpSendPing ){ + assert( isUpSubMsgTailValid(0) ) + isUpSubMsgTailValid(0) := false.B + } .otherwise{ + assert( isUpSubMsgTailValid(1) ) + isUpSubMsgTailValid(1) := false.B + } + } .elsewhen( upRecParser.io.subMsgTailReq.fire ){ + when( isUpRecPing ){ + assert( ~isUpSubMsgTailValid(0) ) + isUpSubMsgTailValid(0) := true.B + } .otherwise{ + assert( ~isUpSubMsgTailValid(1) ) + isUpSubMsgTailValid(1) := true.B + } + } + + + when( upSendGen.io.subMsgTailReq.fire ){ //ready + isUpSendPing := ~isUpSendPing + }.elsewhen( upRecParser.io.subMsgTailReq.fire ){ + isUpRecPing := ~isUpRecPing + } + upRecFifo(0).io.deq <> upSendGen.io.data(0) upRecFifo(1).io.deq <> upSendGen.io.data(1) @@ -346,22 +424,40 @@ abstract class SlaveParserBase extends Module{ trait SlaveParserIndex{ this: SlaveParserBase => - //下行接收 - when( downRecParser.io.subMsgReq.fire & - downRecParser.io.subMsgReq.bits.devIndex === 0.U & - downRecParser.io.subMsgReq.bits.style === 0.U & - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址 - localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U - indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U) - when( isDownRecPing ){ - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U - } .otherwise{ //pong - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + //下行接收 + when( downRecParser.io.subMsgTailReq.fire ){ + when( isDownRecPing & + downSubMsgHeadInfo(0).devIndex === 0.U & + downSubMsgHeadInfo(0).style === 0.U & + downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_INDEX + ){ + localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U + indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U) + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U + } .elsewhen( ~isDownRecPing & + downSubMsgHeadInfo(1).devIndex === 0.U & + downSubMsgHeadInfo(1).style === 0.U & + downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_INDEX + ){ //pong + localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U + indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U) + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } - //上行接收 获取右侧索引号 + // when( downRecParser.io.subMsgHeadReq.fire & + // downRecParser.io.subMsgHeadReq.bits.devIndex === 0.U & + // downRecParser.io.subMsgHeadReq.bits.style === 0.U & + // downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址 + // localDevIndex := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U + // indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgHeadReq.bits.workCnt + 2.U) + // when( isDownRecPing ){ + // downSubMsgHeadInfo(0).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U + // } .otherwise{ //pong + // downSubMsgHeadInfo(1).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U + // } + // } } @@ -371,24 +467,27 @@ trait SlaveParserIndex{ this: SlaveParserBase => trait SlaveParserRW{ this: SlaveParserBase => + val isDownLgcWorked = RegInit(false.B) + val isUpLgcWorked = RegInit(false.B) + //下行接收 - when( downRecParser.io.subMsgReq.fire ){ + when( downRecParser.io.subMsgTailReq.fire ){ when( isDownRecPing ){ //override when( - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & isDownLgcWorked ) ) ) | + ( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) { //自身包//写操作或读写操作) - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } .otherwise{ //pong //override when( - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE ) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE ) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & isDownLgcWorked ) ) ) | + ( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) { //自身包//写操作或读写操作 ) - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } } @@ -398,32 +497,93 @@ trait SlaveParserRW{ this: SlaveParserBase => //写入 SM或寄存器空间 val addrw = Reg(UInt(15.W)) + val logicAddrwNext = Wire( UInt(30.W) ) + val logicAddrw = RegNext(logicAddrwNext) val isWRReg = (addrw(14,11) === "b0000".U) - val isWRSM0 = (addrw(14,11) === "b0001".U) - val isWRSM2 = (addrw(14,11) === "b0011".U) - val isWRSM4 = (addrw(14,11) === "b0101".U) - val isWRSM6 = (addrw(14,11) === "b0111".U) + val isWRSM0 = (addrw(14,11) === "b0001".U) + val isWRSM2 = (addrw(14,11) === "b0011".U) + val isWRSM4 = (addrw(14,11) === "b0101".U) + val isWRSM6 = (addrw(14,11) === "b0111".U) + val downTransLenCnt = RegInit(0.U) val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(0).devIndex === localDevIndex)) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(1).devIndex === localDevIndex)) | - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) - when( downRecParser.io.subMsgReq.fire & ( - downRecParser.io.subMsgReq.bits.devIndex === localDevIndex | - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR - ) - ){ - addrw := downRecParser.io.subMsgReq.bits.address - } .elsewhen( isWrite & downRecParser.io.data.fire ){ - addrw := addrw + 1.U + + val isDownLgcAddrwAcquireTrans = //是否触发地址转换 + (downTransLenCnt === 0.U) & ( (0 until 8).map{ i => + sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) + }.reduce(_|_)) + + val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).pAddr + } + ) + + val acquireDownTransLen = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).length + } + ) + + when( isDownLgcAddrwAcquireTrans ){ //装填计数器 + downTransLenCnt := acquireDownTransLen + } .elsewhen( downRecParser.io.data.fire & downTransLenCnt =/= 0.U){ + downTransLenCnt := downTransLenCnt - 1.U } + when( downRecParser.io.subMsgTailReq.fire ){ + isDownLgcWorked := false.B + } .elsewhen( isDownLgcAddrwAcquireTrans ){ + isDownLgcWorked := true.B + } + + //组合逻辑 + when( downRecParser.io.subMsgHeadReq.fire & ( + (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex + )){//组合逻辑 + logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address ) + } .elsewhen( downRecParser.io.data.fire & ( + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + )){//组合逻辑 + logicAddrwNext := logicAddrw + 1.U + } .otherwise{//组合逻辑 + logicAddrwNext := logicAddrw + } + + when( + ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ){ //常规寻址 + when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填 + addrw := downRecParser.io.subMsgHeadReq.bits.address + } .elsewhen( isWrite & downRecParser.io.data.fire ){ + addrw := addrw + 1.U + } + } .elsewhen( isDownLgcAddrwAcquireTrans & ( + ( downRecParser.io.subMsgHeadReq.fire & (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + )){ + addrw := acquireDownPhyAddrw + } .elsewhen( + isWrite & downRecParser.io.data.fire & ( + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + ) ){ + assert(~isDownLgcAddrwAcquireTrans) + addrw := Mux( downTransLenCnt === 0.U, 0.U, addrw + 1.U ) + } io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire io.lvds.dataw := downRecParser.io.data.bits @@ -445,31 +605,26 @@ trait SlaveParserRW{ this: SlaveParserBase => io.sram_w(3).dataw := downRecParser.io.data.bits - - // val SUBMSG_OPERATOR_BOARDREAD = "hd".U - // val SUBMSG_OPERATOR_BOARDWRITE = "he".U - // val SUBMSG_OPERATOR_BOARDRDWR = "hf".U - //上行接收 - when( upRecParser.io.subMsgReq.fire ){ + when( upRecParser.io.subMsgTailReq.fire ){ when( isUpRecPing ){ //override when( - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ){ //自身包//读或读写 - upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } .otherwise{ //override when( - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ){ //自身包//读或读写 ) - upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } } @@ -478,18 +633,67 @@ trait SlaveParserRW{ this: SlaveParserBase => + val upTransLenCnt = RegInit(0.U) - //读出uSM - val isRead = - ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex) | - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) - ) - ) val addrr = Reg(UInt(15.W)) + val logicAddrrNext = Wire( UInt(30.W) ) + val logicAddrr = RegNext(logicAddrrNext) + + + val isUpLgcAddrrAcquireTrans = //是否触发地址转换 + (upTransLenCnt === 0.U) & ( (0 until 8).map{ i => + sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr) + }.reduce(_|_)) + + val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).pAddr + } + ) + + val acquireUpTransLen = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).length + } + ) + + when( isUpLgcAddrrAcquireTrans & ( + (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + )){ //装填计数器 + upTransLenCnt := acquireUpTransLen + } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){ + upTransLenCnt := upTransLenCnt - 1.U + } + + when( upRecParser.io.subMsgTailReq.fire ){ + isUpLgcWorked := false.B + } .elsewhen( isUpLgcAddrrAcquireTrans ){ + isUpLgcWorked := true.B + } + + //组合逻辑 + when( upRecParser.io.subMsgHeadReq.fire & ( + (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex + )){//组合逻辑 + logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address ) + } .elsewhen( upRecParser.io.data.fire){ + when( + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex ) + ){//组合逻辑 + logicAddrrNext := logicAddrr + 1.U + } .otherwise{ + logicAddrrNext := 0.U + } + } .otherwise{//组合逻辑 + logicAddrrNext := logicAddrr + } + val isRDReg = addrr(14,11) === "b0000".U val isRDSM1 = addrr(14,11) === "b0010".U @@ -497,35 +701,66 @@ trait SlaveParserRW{ this: SlaveParserBase => val isRDSM5 = addrr(14,11) === "b0110".U val isRDSM7 = addrr(14,11) === "b1000".U - val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) | - upRecParser.io.data.fire ) - - when( upRecParser.io.subMsgReq.fire & ( - upRecParser.io.subMsgReq.bits.devIndex === localDevIndex | - upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | - upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR + val isSeqRead = + ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) | + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ) + ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire ) + + val isLgcRead = + ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) + ) + ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire ) + + val isLvdsEnR = isSeqRead | isLgcRead + + + + when( + ((upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgHeadReq.bits.isSeqIndex & upRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ){ - addrr := upRecParser.io.subMsgReq.bits.address - } .elsewhen( isLvdsEnR ){ - addrr := addrr + 1.U + when( upRecParser.io.subMsgHeadReq.fire){ + addrr := upRecParser.io.subMsgHeadReq.bits.address + } .elsewhen(isLvdsEnR){ + addrr := addrr + 1.U + } + } .elsewhen( isUpLgcAddrrAcquireTrans & ( + (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + )){ + addrr := acquireUpPhyAddrr + } .elsewhen( isLvdsEnR & ( + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + )){ + assert(~isUpLgcAddrrAcquireTrans) + addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) } + + val upStreamData = Mux1H(Seq( - isRDReg -> io.lvds.datar, - isRDSM1 -> io.sram_r(0).datar, - isRDSM3 -> io.sram_r(1).datar, - isRDSM5 -> io.sram_r(2).datar, - isRDSM7 -> io.sram_r(3).datar, + isRDReg -> io.lvds.datar, + isRDSM1 -> io.sram_r(0).datar, + isRDSM3 -> io.sram_r(1).datar, + isRDSM5 -> io.sram_r(2).datar, + isRDSM7 -> io.sram_r(3).datar, )) - when( ~isUpRecPing ){ //req fire 后 已经反相 + when( isUpRecPing ){ upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( - ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex, upStreamData, - Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, + ( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) | (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, + Mux( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) ) upRecParser.io.data.ready := upRecFifo(0).io.enq.ready @@ -539,8 +774,8 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.bits := Mux( - ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex, upStreamData, - Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, + ( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) | (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, + Mux( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) ) @@ -588,18 +823,40 @@ trait SlaveParserRW{ this: SlaveParserBase => trait SlaveParserSync{ this: SlaveParserBase => + + // when( upRecParser.io.subMsgTailReq.fire ){ + // when( isUpRecPing ){ + // //override + // when( + // ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + // ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + // ){ //自身包//读或读写 + // upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U + // } + // } .otherwise{ + // //override + // when( + // ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + // ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + // ){ //自身包//读或读写 ) + // upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U + // } + // } + // } + + //下行接收 - when( downRecParser.io.subMsgReq.fire ){ + when( downRecParser.io.subMsgTailReq.fire ){ when( isDownRecPing ){ //override - when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包 - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + when( downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } .otherwise{ //pong //override - when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包 ) - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + when( downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 ) + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } } @@ -640,8 +897,8 @@ trait SlaveParserSync{ this: SlaveParserBase => //下行接收 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | - ( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === SUBMSG_OPERATOR_SYNC ) + ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | + ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) ) val syncCnt = Reg(UInt(4.W)) diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index f18a86b..78fbcc9 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -4,24 +4,17 @@ import chisel3._ import chisel3.util._ -/** - * @param rec 输入来自CDRIn模块的axis格式原始数据 - * @param data 输出解析后的子报文负载 - * @param stateCurr 用于辅助上级SlaveParser模块 - * @param frameReq 输出解析的帧头给上级SlaveParser模块 - * @param subMsgReq 输出解析的子报文头给上级SlaveParser模块 - * @param resp 清模块的STATE_ERROR状态 - * @param isError 输出模块的错误信息触发中断 - */ class SlaveRecParserIO extends Bundle{ val rec = Flipped( Decoupled(new AXIS_Bundle(8)) ) val data = Decoupled(UInt(8.W)) + val stateNext = Output(UInt(4.W)) val stateCurr = Output(UInt(4.W)) val frameReq = Valid( new FrameHeader ) - val subMsgReq = Valid( new SubMsgHeader ) + val subMsgHeadReq = Valid( new SubMsgHeader ) + val subMsgTailReq = Valid( new SubMsgTail ) val resp = Input(Bool()) val isError = Output(Bool()) @@ -35,14 +28,16 @@ class SlaveRecParser extends Module{ val crc = Module(new crc32_8) val STATE_IDLE = 0.U //空闲 - val STATE_HEADER = 1.U //包头 - val STATE_SUBMSG_HEADER = 2.U //子报文头 + val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 + val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型 val STATE_PAYLOAD_DATA = 3.U //子报文数据 - val STATE_CRC = 4.U //CRC校验 - val STATE_ERROR = 5.U // + val STATE_SUBMSG_TAIL = 4.U + val STATE_CRC = 5.U //CRC校验 + val STATE_ERROR = 6.U // + val STATE_WAIT = 7.U - val stateNext = Wire(UInt(4.W)) + val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr io.isError := stateCurr === STATE_ERROR @@ -51,7 +46,8 @@ class SlaveRecParser extends Module{ crc.io.isEnable := io.rec.fire & ( stateCurr === STATE_HEADER | stateCurr === STATE_SUBMSG_HEADER | - stateCurr === STATE_PAYLOAD_DATA + stateCurr === STATE_PAYLOAD_DATA | + stateCurr === STATE_SUBMSG_TAIL ) @@ -79,22 +75,25 @@ class SlaveRecParser extends Module{ val frameLenCnt = Reg(UInt(12.W)) //帧长度计数 - io.frameReq.valid := io.rec.fire & (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER) + io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC) val frameHeader = Reg(new FrameHeader) io.frameReq.bits.frameLenAim := frameHeader.frameLenAim io.frameReq.bits.frameStyle := frameHeader.frameStyle io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata - io.subMsgReq.valid := io.rec.fire & (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA) + io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA) + io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL) + val subMsgHeader = Reg(new SubMsgHeader) + val subMsgTail = Reg(new SubMsgTail) - io.subMsgReq.bits.devIndex := subMsgHeader.devIndex - io.subMsgReq.bits.style := subMsgHeader.style - io.subMsgReq.bits.address := subMsgHeader.address - io.subMsgReq.bits.operator := subMsgHeader.operator - io.subMsgReq.bits.length := subMsgHeader.length - io.subMsgReq.bits.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0) + io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex + io.subMsgHeadReq.bits.style := subMsgHeader.style + io.subMsgHeadReq.bits.address := subMsgHeader.address + io.subMsgHeadReq.bits.operator := subMsgHeader.operator + io.subMsgHeadReq.bits.length := subMsgHeader.length | io.rec.bits.tdata(7,0) + io.subMsgTailReq.bits.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0) when( io.rec.fire ){ when( stateCurr =/= stateNext ){ @@ -110,7 +109,8 @@ class SlaveRecParser extends Module{ frameLenCnt := 0.U } .elsewhen( ( stateCurr === STATE_SUBMSG_HEADER ) || - ( stateCurr === STATE_PAYLOAD_DATA ) + ( stateCurr === STATE_PAYLOAD_DATA ) || + ( stateCurr === STATE_SUBMSG_TAIL ) ){ frameLenCnt := frameLenCnt + 1.U } @@ -129,35 +129,43 @@ class SlaveRecParser extends Module{ when( io.rec.fire ){ - when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){ - frameHeader.frameLenAim := io.rec.bits.tdata << 4 - } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){ - frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4) - frameHeader.frameStyle := io.rec.bits.tdata(1,0) - } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){ - frameHeader.frameInfo := io.rec.bits.tdata << 8 - } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){ - frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata + when( stateCurr === STATE_HEADER ){ + when( lengthCnt === 0.U ){ + frameHeader.frameLenAim := io.rec.bits.tdata << 4 + } .elsewhen( lengthCnt === 1.U ){ + frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4) + frameHeader.frameStyle := io.rec.bits.tdata(1,0) + } .elsewhen( lengthCnt === 2.U ){ + frameHeader.frameInfo := io.rec.bits.tdata << 8 + } .elsewhen( lengthCnt === 3.U ){ + frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata + } + } + + when( stateCurr === STATE_SUBMSG_HEADER ){ + when(lengthCnt === 0.U ){ + subMsgHeader.devIndex := io.rec.bits.tdata << 6 + } .elsewhen( lengthCnt === 1.U ){ + subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2) + subMsgHeader.style := io.rec.bits.tdata(1,0) + } .elsewhen( lengthCnt === 2.U ){ + subMsgHeader.address := io.rec.bits.tdata << 8 + } .elsewhen( lengthCnt === 3.U ){ + subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata + } .elsewhen( lengthCnt === 4.U ){ + subMsgHeader.operator := io.rec.bits.tdata(7,4) + subMsgHeader.length := io.rec.bits.tdata(3,0) << 8 + } .elsewhen( lengthCnt === 5.U ){ + subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0) + } } - when( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 0.U ){ - subMsgHeader.devIndex := io.rec.bits.tdata << 6 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 1.U ){ - subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2) - subMsgHeader.style := io.rec.bits.tdata(1,0) - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 2.U ){ - subMsgHeader.address := io.rec.bits.tdata << 8 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 3.U ){ - subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 4.U ){ - subMsgHeader.operator := io.rec.bits.tdata(7,4) - subMsgHeader.length := io.rec.bits.tdata(3,0) << 8 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 5.U ){ - subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0) - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 6.U ){ - subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 7.U ){ - subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0) + when( stateCurr === STATE_SUBMSG_TAIL ){ + when(lengthCnt === 0.U ){ + subMsgTail.workCnt := io.rec.bits.tdata << 8 + } .elsewhen( lengthCnt === 1.U ){ + subMsgTail.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0) + } } } @@ -180,18 +188,24 @@ class SlaveRecParser extends Module{ )), STATE_HEADER ), ( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, - Mux( lengthCnt === (8-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER ) + Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER ) ), STATE_SUBMSG_HEADER), - ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR, - Mux( lengthCnt === ( subMsgHeader.length - 1.U), - Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER - ), STATE_PAYLOAD_DATA ) + ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR, + Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA ) ), STATE_PAYLOAD_DATA), + + ( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, + Mux( lengthCnt === ( (2 - 1).U), + Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER + ),STATE_SUBMSG_TAIL ) + ), STATE_SUBMSG_TAIL), + ( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast, Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC ), ( stateCurr === STATE_ERROR ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ), + ( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_WAIT ) )) diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 96f6f82..d121908 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -8,21 +8,19 @@ class SubMsgTxInfo extends SubMsgHeader{ val source = UInt(2.W) } -/** - * @param data 连接上级模块SlaveParser down/up-RecFifo 的pingpong缓冲区的deq，准备用于发送转发 - * @param frameReq 连接上级模块SlaveParser请求的帧头结构体 - * @param subMsgReq 连接上级模块SlaveParser请求的子报文结构体 - * @param send 输出axis格式的发送输出数据到CDRout模块 - * @param stateCurr 输出内部状态机状态给上级模块SlaveParser辅助判断（无意义） - */ + class SlaveSendGenIO extends Bundle{ val data = Vec(2, Flipped( Decoupled(UInt(8.W)) ) ) + + val frameReq = Flipped(Decoupled( new FrameHeader )) - val subMsgReq = Flipped(Decoupled( new SubMsgTxInfo )) + val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo )) + val subMsgTailReq = Flipped(Decoupled( new SubMsgTail )) val send = Decoupled(new AXIS_Bundle(8)) + val isError = Output(Bool()) val stateCurr = Output(UInt(3.W)) } @@ -42,17 +40,21 @@ class SlaveSendGen extends Module{ val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型 val STATE_SUBMSG_HEADER = 2.U val STATE_SUBMSG_DATA = 3.U - val STATE_CRC = 4.U //CRC校验 - val STATE_WAIT = 5.U + val STATE_SUBMSG_TAIL = 4.U + val STATE_CRC = 5.U //CRC校验 + val STATE_WAIT = 6.U val stateNext = Wire(UInt(3.W)) val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr + io.isError := false.B//stateCurr === STATE_ERROR + crc.io.isEnable := io.send.fire & ( stateCurr === STATE_FRAME_HEADER | stateCurr === STATE_SUBMSG_HEADER | - stateCurr === STATE_SUBMSG_DATA + stateCurr === STATE_SUBMSG_DATA | + stateCurr === STATE_SUBMSG_TAIL ) @@ -64,22 +66,22 @@ class SlaveSendGen extends Module{ val frameInfo = Reg(new FrameHeader) - val subMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } + val subMsgHeadInfo = Reg(new SubMsgTxInfo) + val subMsgTailInfo = Reg(new SubMsgTail) + - val isPingFill = RegInit(false.B) - val isPingEmit = RegInit(false.B) when( io.frameReq.fire ){ frameInfo := io.frameReq.bits } - when( io.subMsgReq.fire ){ - when( isPingFill ){ - subMsgInfo(0) := io.subMsgReq.bits - } .otherwise{ - subMsgInfo(1) := io.subMsgReq.bits - } + when( io.subMsgHeadReq.fire ){ + subMsgHeadInfo := io.subMsgHeadReq.bits + } + + when( io.subMsgTailReq.fire ){ + subMsgTailInfo := io.subMsgTailReq.bits } @@ -90,7 +92,7 @@ class SlaveSendGen extends Module{ when( io.send.fire ){ when( stateCurr === STATE_FRAME_HEADER ){ frameLenCnt := 0.U - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA ){ + } .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA || stateCurr === STATE_SUBMSG_TAIL ){ frameLenCnt := frameLenCnt + 1.U } } @@ -104,35 +106,39 @@ class SlaveSendGen extends Module{ - val subMsgInfoSel = Mux( isPingEmit, subMsgInfo(0), subMsgInfo(1) ) - - - io.frameReq.ready := true.B - io.subMsgReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER - + io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER + io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL + assert( ~(io.subMsgTailReq.ready & ~io.subMsgTailReq.valid) ) stateNext := Mux1H(Seq( (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), (stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux( frameInfo.frameStyle === FRAME_STYLE_COMMON, - Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), + Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), STATE_CRC ), STATE_FRAME_HEADER), STATE_FRAME_HEADER ), - (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), + (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), + (stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire, - Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文 + Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文 + STATE_SUBMSG_DATA ), + + (stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire, + Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾 Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC - Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文 - STATE_SUBMSG_DATA - ), STATE_SUBMSG_DATA ), + Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文 + STATE_SUBMSG_TAIL + ), STATE_SUBMSG_TAIL ), + (stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC), - (stateCurr === STATE_WAIT) -> Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), + // (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR), + (stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), )) - io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 0.U) - io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 1.U) + io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U) + io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U) assert( ~(io.data(0).ready & ~io.data(0).valid) ) assert( ~(io.data(1).ready & ~io.data(1).valid) ) @@ -142,7 +148,8 @@ class SlaveSendGen extends Module{ io.send.valid := (stateCurr === STATE_FRAME_HEADER) | (stateCurr === STATE_SUBMSG_HEADER) | - (stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgInfoSel.source === 0.U) | (io.data(1).valid & subMsgInfoSel.source === 1.U) )) | + (stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgHeadInfo.source === 0.U) | (io.data(1).valid & subMsgHeadInfo.source === 1.U) )) | + (stateCurr === STATE_SUBMSG_TAIL) | (stateCurr === STATE_CRC) @@ -154,25 +161,29 @@ class SlaveSendGen extends Module{ )) val tdata_submsg_header = Mux1H(Seq( - (lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6), - (lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style), - (lengthCnt === 2.U) -> subMsgInfoSel.address(15,8), - (lengthCnt === 3.U) -> subMsgInfoSel.address(7,0), - (lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)), - (lengthCnt === 5.U) -> subMsgInfoSel.length(7,0), - (lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8), - (lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0), + (lengthCnt === 0.U) -> subMsgHeadInfo.devIndex(13,6), + (lengthCnt === 1.U) -> Cat( subMsgHeadInfo.devIndex(5,0), subMsgHeadInfo.style), + (lengthCnt === 2.U) -> subMsgHeadInfo.address(15,8), + (lengthCnt === 3.U) -> subMsgHeadInfo.address(7,0), + (lengthCnt === 4.U) -> Cat(subMsgHeadInfo.operator, subMsgHeadInfo.length(11,8)), + (lengthCnt === 5.U) -> subMsgHeadInfo.length(7,0), )) val tdata_submsg_data = Mux1H(Seq( - (subMsgInfoSel.source === 0.U) -> io.data(0).bits, - (subMsgInfoSel.source === 1.U) -> io.data(1).bits, + (subMsgHeadInfo.source === 0.U) -> io.data(0).bits, + (subMsgHeadInfo.source === 1.U) -> io.data(1).bits, + )) + + val tdata_submsg_tail = Mux1H(Seq( + (lengthCnt === 0.U) -> subMsgTailInfo.workCnt(15,8), + (lengthCnt === 1.U) -> subMsgTailInfo.workCnt( 7,0), )) crc.io.dataIn := Mux1H(Seq( (stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header, (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header, (stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data, + (stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail, )) @@ -187,6 +198,7 @@ class SlaveSendGen extends Module{ (stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header, (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header, (stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data, + (stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail, (stateCurr === STATE_CRC) -> tdata_crc, )) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 490b9a4..adfb873 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -17,9 +17,19 @@ //`define ENABLE_BC_RW_TEST `define ENABLE_SYNC_TEST -`define ENABLE_SYNC_SIG0_TEST -`define ENABLE_SYNC_SIG1_TEST -`define ENABLE_RESET_TEST +//`define ENABLE_SYNC_SIG0_TEST +//`define ENABLE_SYNC_SIG1_TEST +//`define ENABLE_RESET_TEST + +//`define ENABLE_EBMMU_TC1_TEST +//`define ENABLE_EBMMU_TC2_TEST +//`define ENABLE_EBMMU_TC3_TEST +//`define ENABLE_EBMMU_TC4_TEST +//`define ENABLE_EBMMU_TC5_TEST +//`define ENABLE_EBMMU_TC6_TEST +//`define ENABLE_EBMMU_TC7_TEST + +`define ENABLE_WD_TC1_TEST module ShinTopSpiTb( @@ -233,7 +243,7 @@ ShinTop s_ShinTop_slv3( initial begin clock = 0; clk8x = 0; - reset = 0; + reset = 1; _reset_deactive = 1'b0; @@ -422,7 +432,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in $realtime, ((sidx >= 5)? ((sidx >= 10)? (sidx - 10):(sidx - 5)):sidx), txBuf[0], txBuf[1], ((txBuf[2] == 0)? "Write":" Read"), slength); - if ( ((saddress == 16'h0800) + if ( ((saddress == 16'h0800) || (saddress == 16'h1000) || (saddress == 16'h1800) || (saddress == 16'h2000) @@ -443,7 +453,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in $fwrite(spidata_file, "\n"); _pos = 4 + _pos; for (; _pos < slength; ) begin - for (integer _k = 0; _k < 8; _k++) begin + for (integer _k = 0; _k < 6; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); _len = txBuf[_pos + 5] + (txBuf[_pos + 4] & 8'h0f) * 256; @@ -452,9 +462,38 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in _len = rxBuf[_pos + 5] + (rxBuf[_pos + 4] & 8'h0f) * 256; end end + + begin:PRINT_PKT_COMMENT + integer dev; + integer addr_type; + integer addr; + integer cmd; + integer len; + + if (scmd == 0) begin + addr_type = txBuf[_pos + 1] & 8'h3; + dev = (txBuf[_pos] >> 2) * 256 + ((txBuf[_pos + 1] >> 2) & 8'hff); + addr = txBuf[_pos + 2] * 256 + (txBuf[_pos + 3] & 8'hff); + cmd = (txBuf[_pos + 4] >> 4) & 8'h0f; + len = (txBuf[_pos + 4] & 8'h0f) * 256 + (txBuf[_pos + 5] & 8'hff); + end else begin + addr_type = rxBuf[_pos + 1] & 8'h3; + dev = (rxBuf[_pos] >> 2) * 256 + ((rxBuf[_pos + 1] >> 2) & 8'hff); + addr = rxBuf[_pos + 2] * 256 + (rxBuf[_pos + 3] & 8'hff); + cmd = (rxBuf[_pos + 4] >> 4) & 8'h0f; + len = (rxBuf[_pos + 4] & 8'h0f) * 256 + (rxBuf[_pos + 5] & 8'hff); + end + + if (addr_type == 0) + $fwrite(spidata_file, "// type:%3d dev:%3d addr:0x%04x cmd:0x%1x len:%3d", addr_type, dev, addr[15:0], cmd[3:0], len); + else begin + addr = dev * 65536 + addr; + $fwrite(spidata_file, "// type:%3d addr:0x%08x cmd:0x%1x len:%3d", addr_type, addr, cmd[3:0], len); + end + end $fwrite(spidata_file, "\n{{ "); - _pos = _pos + 8; + _pos = _pos + 6; for (integer _k = 0; _k < _len; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); @@ -469,6 +508,16 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in end $fwrite(spidata_file, "}}\n"); _pos = _pos + _len; + + for (integer _k = 0; _k < 2; _k++) begin + if (scmd == 0) begin + $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); + end else begin + $fwrite(spidata_file, "%02h ", rxBuf[_k + _pos]); + end + end + _pos = _pos + 2; + $fwrite(spidata_file, "\n"); end end else begin for (integer i=0; i 2048: + if pkt_len > 2044: print('Error, bad pkt_len:', pkt_len) return @@ -116,14 +116,6 @@ class GenPkt(object): self.pkt_buf.append(temp & 0xff) i = i + 1 - #工作计数 - #self.pkt_buf[i] = 0 - self.pkt_buf.append(0) - i = i + 1 - #self.pkt_buf[i] = 0 - self.pkt_buf.append(0) - i = i + 1 - #数据 if sp[6] == None: for _k in range(sp[5]): @@ -136,6 +128,14 @@ class GenPkt(object): i = i + sp[5] + #工作计数 + #self.pkt_buf[i] = 0 + self.pkt_buf.append(0) + i = i + 1 + #self.pkt_buf[i] = 0 + self.pkt_buf.append(0) + i = i + 1 + f = open(filename, "wt+") if filetype == 1: for md in self.sub_pkt: @@ -231,7 +231,67 @@ def genCheckInsertTimeCode(): return '''\n//检查替换时间戳替换地址\n'''\ + '''$fdisplay(spidata_file, "--检查时间戳插入");\n'''\ + '''spi_trans( (16'h24), (`SPI_READ), (2), (`IF_IDX(0)) ); //检查替换时间戳替换地址寄存器\n''' + + +def genIFRwDataCode(dev, addr, isWrite = False, data_len=0, data = None): + if isWrite == True: + if (data == None) or (len(data) == 0): + data=list() + code = '' + idx = 3 + for item in data: + code = code + '''txBuf[%d]=8'h%02x;\n'''%(idx, item & 0xff) + idx = idx + 1 + + code = code + '''spi_trans( (16'h%04x), (`SPI_WRITE), (%d), (`IF_IDX(%d)) );\n'''%(addr, data_len, dev) + return code + else: + code = '' + code = code + '''spi_trans( (16'h%04x), (`SPI_READ), (%d), (`IF_IDX(%d)) );\n'''%(addr, data_len, dev) + return code + +def genSlvSMWriteData(dev, sm, data_len, data = None): + smaddr = list() + for i in range(8): + smaddr.append(0x300 + i * 4 + 2) + if not ((sm == 1) or (sm == 3) or (sm == 5) or (sm == 7)): + #写入数据，lvds读；这个空间是lvds写，mcu读 + return '' + if data_len > 2032: + return '' + + if (data != None) and (len(data) != 0) and (len(data) < data_len): + return '' + + if (data == None) or (len(data) == 0): + data = list() + for i in range(data_len): + data.append((i + dev) & 0xff) + + code = '''txBuf[3] = 8'h%02x;\n'''%(data_len & 0xff, )\ + + '''txBuf[4] = 8'h%02x;\n'''%(int(data_len/256) & 0xff,)\ + + '''spi_trans((16'h0%04x), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%(smaddr[sm], dev) + + for i in range(data_len): + code = code + '''txBuf[%d + 3] = 8'h%02x;\n'''%(i, data[i]) + + code = code + '''spi_trans( (16'h%04x), (`SPI_WRITE), (%d), (`IF_IDX(%d)) );\n'''%(0x800 + sm * 2048, data_len, dev) + return code + +def genSlvSMReadData(dev, sm, data_len): + if not ((sm == 0) or (sm == 2) or (sm == 4) or (sm == 6)): + #写入数据，lvds读；这个空间是lvds写，mcu读 + return '' + if data_len > 2032: + return '' + + code = "" + code = code + '''spi_trans( (16'h%04x), (`SPI_READ), (%d), (`IF_IDX(%d)) );\n'''%(0x800 + sm * 2048, data_len, dev) + + return code + + if __name__ == '__main__': genPkt = GenPkt() @@ -418,12 +478,17 @@ if __name__ == '__main__': #>>>>>>普通数据包2 genPkt.clean() genPkt.setPktType(0) - + + genPkt.addBeforeExc( genSlvSMWriteData(3, 1, 129) + + genSlvSMWriteData(4, 1, 140) + + genSlvSMWriteData(1, 1, 128) + + genSlvSMWriteData(2, 1, 152)) + #subPkt参数：索引、索引类型、地址、命令、长度、数据 - genPkt.addSubPkt(3, 0, 0x3000, 0x0, 129, b"\0"*129) - genPkt.addSubPkt(4, 0, 0x4000, 0x0, 140, b"\0"*140) + genPkt.addSubPkt(3, 0, 0x1000, 0x0, 129, b"\0"*129) + genPkt.addSubPkt(4, 0, 0x1000, 0x0, 140, b"\0"*140) genPkt.addSubPkt(1, 0, 0x1000, 0x0, 128, b"\0"*128) - genPkt.addSubPkt(2, 0, 0x2000, 0x0, 152, b"\0"*152) + genPkt.addSubPkt(2, 0, 0x1000, 0x0, 152, b"\0"*152) genPkt.addSubPkt(1, 0, 0x0306, 0x0, 2, b"\0"*2) genPkt.addSubPkt(2, 0, 0x030e, 0x0, 2, b"\0"*2) genPkt.addSubPkt(3, 0, 0x0316, 0x0, 2, b"\0"*2) @@ -470,15 +535,11 @@ if __name__ == '__main__': genPkt.clean() genPkt.setPktType(0) - - - - #subPkt参数：索引、索引类型、地址、命令、长度、数据 genPkt.addSubPkt(0x0, 0, random.randint(0, 65535), 0xc, 12, b'\0'*12) - genPkt.addBeforeExc(genEnableInsertTimeCode(0xc)) + genPkt.addBeforeExc(genEnableInsertTimeCode(0xa)) gen_file_def = "sync_pkt" sm_idx = 0 @@ -725,7 +786,7 @@ if __name__ == '__main__': data[19] = '''(_temp_time >> 24) & 8'hff''' data[24] = 0x00 #地址0x138, sync周期 4B - data[25] = 0x04 #地址0x139 + data[25] = 0x04 #地址0x139genPkt.addBeforeExc( data[28] = 0x0 #sync1偏移 data[29] = 0x0 @@ -844,7 +905,835 @@ if __name__ == '__main__': - - + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x00 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0200, 0x1, 10, data) + + + data = [0,] * 30 + data[0] = 0x0a + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x0200, 0x1, 10, data) + + + data = [0,] * 30 + + data[0] = 0x14 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0200, 0x1, 10, data) + + data = [0,] * 30 + + data[0] = 0x1e + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x0200, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc1_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>读取EB-MMU的设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 40 + + genPkt.addSubPkt(0x01, 0, 0x0200, 0x0, 10, data) + genPkt.addSubPkt(0x02, 0, 0x0200, 0x0, 10, data) + genPkt.addSubPkt(0x03, 0, 0x0200, 0x0, 10, data) + genPkt.addSubPkt(0x04, 0, 0x0200, 0x0, 10, data) + + gen_file_def = "ebmmu_tc1_seq_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 40 + + genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 40, data) + + gen_file_def = "ebmmu_tc1_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x00 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x020a, 0x1, 10, data) + + + data = [0,] * 30 + data[0] = 0x10 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x020a, 0x1, 10, data) + + + data = [0,] * 30 + + data[0] = 0x20 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x020a, 0x1, 10, data) + + data = [0,] * 30 + + data[0] = 0x30 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x020a, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc2_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>读取数据 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 40 + + genPkt.addSubPkt(0x01, 0, 0x0000, 0x0, 16, data) + genPkt.addSubPkt(0x02, 0, 0x0000, 0x0, 16, data) + genPkt.addSubPkt(0x03, 0, 0x0000, 0x0, 16, data) + genPkt.addSubPkt(0x04, 0, 0x0000, 0x0, 16, data) + + gen_file_def = "ebmmu_tc2_seq_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 100 + + genPkt.addSubPkt(0x2000, 2, 0x0000, 0x0, 0x40, data) + + gen_file_def = "ebmmu_tc2_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x1e + 0xa + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0c + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0214, 0x1, 10, data) + + + data = [0,] * 30 + data[0] = 0x1e + 0xa + 0x0c + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0c + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x0214, 0x1, 10, data) + + + data = [0,] * 30 + + data[0] = 0x1e + 0xa + 0x0c + 0x0c + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0c + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0214, 0x1, 10, data) + + data = [0,] * 30 + + data[0] = 0x1e + 0xa + 0x0c + 0x0c + 0x0c + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0c + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x0214, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc3_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 150 + + genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 0x0c * 4 + 0x28, data) + + gen_file_def = "ebmmu_tc3_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + genPkt.addBeforeExc( genSlvSMWriteData(1, 1, 0x80) + + genSlvSMWriteData(2, 3, 0x98) + + genSlvSMWriteData(3, 5, 0x81) + + genSlvSMWriteData(4, 7, 0x8c)) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x58 #0x1e + 0xa + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x10 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x021e, 0x1, 10, data) + + + data = [0,] * 30 + addr = 0x58 + 0x80 + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x20 + + data[6] = 0x98 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x021e, 0x1, 10, data) + + + data = [0,] * 30 + addr = 0x58 + 0x80 + 0x98 + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x30 + + data[6] = 0x81 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x021e, 0x1, 10, data) + + data = [0,] * 30 + + addr = 0x58 + 0x80 + 0x98 + 0x81 + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x40 + + data[6] = 0x8c + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x021e, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc4_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 550 + + genPkt.addSubPkt(0x1000, 2, 0x0058, 0x0, 0x80+0x98+0x81+0x8c, data) + + gen_file_def = "ebmmu_tc4_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 550 + + genPkt.addSubPkt(0x1000, 2, 0x0058, 0x0, 0x80+0x98+0x81+0x8c, data) + + gen_file_def = "ebmmu_tc5_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #-------------------------------------------------------------------------- + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU,测试用例6 + genPkt.clean() + genPkt.setPktType(0) + + addr_off = 0x58 + 0x80 + 0x98 + 0x81 + 0x8c + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + addr = addr_off + 0x0 + #print(hex(addr)) + data[0] = (addr & 0xff) + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x0228, 0x1, 10, data) + + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 2 + data[0] = 0x80 + data[1] = 0x00 + genPkt.addSubPkt(0x0, 0, 0x302, 0xe, 2, data) + + gen_file_def = "ebmmu_tc6_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 0x80 * 4 + for i in range(0x80 * 4): + if i < 0x80: + data[i] = i & 0xff + elif i < 0x80+0x80: + data[i] = (i + 2 - 0x80) & 0xff + elif i < 0x80+0x80+0x80: + data[i] = (i + 3 - 0x80 - 0x80) & 0xff + else: + data[i] = (i + 5 - 0x80 - 0x80 - 0x80) & 0xff + + genPkt.addSubPkt(0x1000, 2, addr_off, 0x1, 0x80 * 4, data) + + gen_file_def = "ebmmu_tc6_write" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + +genSlvSMReadData(1, 0, 0x80) + +genSlvSMReadData(2, 0, 0x80) + +genSlvSMReadData(3, 0, 0x80) + +genSlvSMReadData(4, 0, 0x80)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #-------------------------------------------------------------------------- + #>>>>>>设置EB-MMU,测试用例7 + genPkt.clean() + genPkt.setPktType(0) + + addr_off = 0x58 + 0x80 + 0x98 + 0x81 + 0x8c + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + addr = addr_off + 0x0 + #print(hex(addr)) + data[0] = (addr & 0xff) + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x00 + genPkt.addSubPkt(0x2, 0, 0x0228, 0x1, 10, data) + + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x00 + genPkt.addSubPkt(0x4, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 2 + data[0] = 0x80 + data[1] = 0x00 + genPkt.addSubPkt(0x0, 0, 0x302, 0xe, 2, data) + + gen_file_def = "ebmmu_tc7_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 0x80 * 4 + for i in range(0x80 * 4): + if i < 0x80: + data[i] = i & 0xff + elif i < 0x80+0x80: + data[i] = (i + 2 - 0x80) & 0xff + elif i < 0x80+0x80+0x80: + data[i] = (i + 3 - 0x80 - 0x80) & 0xff + else: + data[i] = (i + 5 - 0x80 - 0x80 - 0x80) & 0xff + + genPkt.addSubPkt(0x1000, 2, addr_off, 0x1, 0x80 * 4, data) + + gen_file_def = "ebmmu_tc7_write" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + +genSlvSMReadData(1, 0, 0x80) + +genSlvSMReadData(2, 0, 0x80) + +genSlvSMReadData(3, 0, 0x80) + +genSlvSMReadData(4, 0, 0x80)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #-------------------------------------------------------------------------- + #>>>>>> 测试用例1 看门狗测试 + genPkt.clean() + genPkt.setPktType(0) + + data = 1<<1 ##使能看门狗1 + data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] + + data = 0x0010 ##看门狗的超时值 + data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] + + data = 0xffffffff ##清除中断 + data2 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] + + genPkt.addBeforeExc( genIFRwDataCode(1, 0x404, True, 4, data0) + + genIFRwDataCode(1, 0x40C, True, 4, data1) + + genIFRwDataCode(1, 0x078, True, 4, data2) + + genIFRwDataCode(2, 0x078, True, 4, data2) + + genIFRwDataCode(3, 0x078, True, 4, data2) + + genIFRwDataCode(4, 0x078, True, 4, data2) + + genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff]) + + genIFRwDataCode(0, 0x074, False, 0x04) + + genIFRwDataCode(1, 0x074, False, 0x04) + + genIFRwDataCode(2, 0x074, False, 0x04) + + genIFRwDataCode(3, 0x074, False, 0x04) + + genIFRwDataCode(4, 0x074, False, 0x04) + + genIFRwDataCode(1, 0x400, False, 0x04)) + #genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])) + + data = [0,] * 2 + data[0] = 0x80 + data[1] = 0x00 + genPkt.addSubPkt(0x0, 0, 0x302, 0xe, 2, data) + + data = [0,] * 0x50 + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + genPkt.addSubPkt(1, 0, 0x800, 0x1, 0x50, data) + + gen_file_def = "wd_tc1" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + +genIFRwDataCode(1, 0x800, False, 0x80) + +genIFRwDataCode(0, 0x074, False, 0x04) + +genIFRwDataCode(1, 0x074, False, 0x04) + +genIFRwDataCode(2, 0x074, False, 0x04) + +genIFRwDataCode(3, 0x074, False, 0x04) + +genIFRwDataCode(4, 0x074, False, 0x04) + +genIFRwDataCode(1, 0x400, False, 0x04)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) +