From 731136a35bc97f11cfcd7b692d8b29eff36ca9d6 Mon Sep 17 00:00:00 2001 From: bacon Date: Mon, 9 Jun 2025 18:02:32 +0800 Subject: [PATCH 01/41] =?UTF-8?q?=E9=87=87=E7=94=A8=E6=96=B0=E7=9A=84?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B=E6=B5=8B=E8=AF=95=E5=90=8C?= =?UTF-8?q?=E6=AD=A5,=E6=9A=82=E6=97=B6=E6=88=90=E5=8A=9F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 490b9a4..a96eac1 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -10,11 +10,11 @@ //`define ENABLE_EXCHG_DATA_SEQ0_TEST //`define ENABLE_EXCHG_DATA_SEQ1_TEST //`define ENABLE_EXCHG_DATA_SEQ2_TEST -//`define ENABLE_EXCHG_DATA_SEQ3_TEST +`define ENABLE_EXCHG_DATA_SEQ3_TEST //`define ENABLE_BC_R_TEST //`define ENABLE_BC_W_TEST -//`define ENABLE_BC_RW_TEST +`define ENABLE_BC_RW_TEST `define ENABLE_SYNC_TEST `define ENABLE_SYNC_SIG0_TEST @@ -1251,11 +1251,13 @@ initial begin `include "sm2_pkt.vh" + $fdisplay(spidata_file, "\n\n测试用例：测试同步(sync)和同步输出(sync_out)"); //设置SM1在写入 0x18 len触发enq `include "sync_pkt.vh" + /* #1000 $fdisplay(spidata_file, "\n\n测试用例：测试同步信号(电平)"); @@ -1267,7 +1269,6 @@ initial begin spi_trans( (16'h0100), (`SPI_READ), (16'h48), (`IF_IDX(3)) ); spi_trans( (16'h0100), (`SPI_READ), (16'h48), (`IF_IDX(4)) ); - #100000 //清脉冲 txBuf[0+3] = 0; //负载0x122 sync0脉冲宽度 @@ -1282,8 +1283,8 @@ initial begin spi_trans( (16'h0122), (`SPI_WRITE), (8), (`IF_IDX(2)) ); //slv2 spi_trans( (16'h0122), (`SPI_WRITE), (8), (`IF_IDX(3)) ); //slv2 spi_trans( (16'h0122), (`SPI_WRITE), (8), (`IF_IDX(4)) ); //slv2 - - /* + */ + `include "sync_sig3_pkt.vh" //spi_trans( (16'h0100), (`SPI_READ), (32), (`IF_IDX(0)) ); @@ -1291,7 +1292,7 @@ initial begin spi_trans( (16'h0100), (`SPI_READ), (16'h48), (`IF_IDX(2)) ); spi_trans( (16'h0100), (`SPI_READ), (16'h48), (`IF_IDX(3)) ); spi_trans( (16'h0100), (`SPI_READ), (16'h48), (`IF_IDX(4)) ); - */ + end `endif From 9f0f232616a84ade1c239d7575cdf8e6993d933a Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 10 Jun 2025 17:20:46 +0800 Subject: [PATCH 02/41] =?UTF-8?q?mmu=E7=9A=84=E8=AF=BB=E5=86=99=E8=A1=8C?= =?UTF-8?q?=E4=B8=BA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 63 ++++++++++++++++--- 1 file changed, 56 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index fb034aa..662e1cb 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -3,6 +3,19 @@ package BACK import chisel3._ import chisel3.util._ + +class EBMMU_Bundle extends Bundle{ + val lAddr = UInt(30.W) + val pAddr = UInt(16.W) + val length = UInt(16.W) + val op = UInt(8.W) + val isEnable = Bool() + + def EBMMU_OP_RD = op === 1.U + def EBMMU_OP_WR = op === 2.U + def EBMMU_OP_RW = op === 3.U +} + class CommonRegisterBundle extends Bundle{ val mstOrSlv = UInt(2.W) def modeSel:Bool = mstOrSlv === "h1".U @@ -72,13 +85,7 @@ class SlaveRegisterBundle extends Bundle{ // val nodeSetAddr = UInt(16.W) - // val ebmmu = Vec(8, new Bundle{ - // val logicAddr = UInt(32.W) - // val length = UInt(16.W) - // val phyAddr = UInt(32.W) - // val op = UInt(2.W) - // val enable = Bool() - // }) + val ebmmu = Vec(8, new EBMMU_Bundle) // val intStatus = UInt(16.W) // val mb = Vec(8, new Bundle{ @@ -364,6 +371,21 @@ abstract class InterfaceBase extends Module{ ( 0 until 128 ).map{ i => ( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i) } ++ + ( 0 until 8 ).map{ i => + ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0), + ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8), + ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16), + ( ( addr === ( "h203".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(29,24), + + ( ( addr === ( "h204".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr( 7, 0), + ( ( addr === ( "h205".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr(15, 8), + + ( ( addr === ( "h206".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length( 7, 0), + ( ( addr === ( "h207".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length(15, 8), + + ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op, + ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable, + } ++ ( 0 until 8 ).map{ i => ( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0) } ++ @@ -725,6 +747,33 @@ trait InterfaceLVDSop{ this: InterfaceBase => } } } + + + ( 0 until 8 ).map{ i => + sReg.ebmmu(i).lAddr := Cat( + RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ), + ) + + sReg.ebmmu(i).pAddr := Cat( + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ), + ) + + sReg.ebmmu(i).length := Cat( + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ), + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ), + ) + + sReg.ebmmu(i).op := + RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) + + sReg.ebmmu(i).isEnable := + RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) ) + } + } trait InterfaceSync{ this: InterfaceBase => From 11f2f701f9584a908dbfc23d0e4c621a7b43d2ea Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 16 Jun 2025 17:40:55 +0800 Subject: [PATCH 03/41] =?UTF-8?q?ebmmu=E5=9C=B0=E5=9D=80=E7=BF=BB=E8=AF=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 4 +- src/main/scala/backBoard/shin/ShinTop.scala | 1 + .../scala/backBoard/shin/SlaveParser.scala | 176 +++++++++++++++--- 3 files changed, 148 insertions(+), 33 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 662e1cb..7cee3a9 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -371,7 +371,7 @@ abstract class InterfaceBase extends Module{ ( 0 until 128 ).map{ i => ( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i) } ++ - ( 0 until 8 ).map{ i => + ( 0 until 8 ).map{ i => Seq( ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0), ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8), ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16), @@ -385,7 +385,7 @@ abstract class InterfaceBase extends Module{ ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op, ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable, - } ++ + )}.reduce(_++_) ++ ( 0 until 8 ).map{ i => ( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0) } ++ diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 8796ce8..0476b00 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -329,6 +329,7 @@ trait ShinTopSlave{ this: ShinTopBase => } slaveParser.io.cReg := interface.io.cReg + slaveParser.io.sReg := interface.io.sReg when( interface.io.cReg.modeSel === false.B ){ diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 9113e9d..23c08b1 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -17,6 +17,9 @@ class SubMsgHeader extends Bundle{ val operator = UInt(4.W) //子报文命令类型 val length = UInt(12.W) //子报文负载长度 val workCnt = UInt(16.W) //子报文工作计数 + + def isSeqIndex = style === 0.U + def isLgcIndex = style === 2.U } @@ -65,6 +68,7 @@ class SlaveParserIO extends Bundle{ val isLoop = Output(Bool()) val cReg = Input(new CommonRegisterBundle) + val sReg = Input(new SlaveRegisterBundle) val lvds = new RegAccessInterfaceIO @@ -75,6 +79,8 @@ class SlaveParserIO extends Bundle{ abstract class SlaveParserBase extends Module{ val io: SlaveParserIO = IO(new SlaveParserIO) + val sReg = io.sReg + val FRAME_STYLE_COMMON = 0.U @@ -376,6 +382,16 @@ trait SlaveParserIndex{ this: SlaveParserBase => trait SlaveParserRW{ this: SlaveParserBase => + // val isSeqIndexMatch = + // (downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex) + + // val downLgcAddress = Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) + // val isLgcIndexMatch = + // (downRecParser.io.subMsgReq.bits.isLgcIndex & + + + + //下行接收 when( downRecParser.io.subMsgReq.fire ){ when( isDownRecPing ){ @@ -403,32 +419,84 @@ trait SlaveParserRW{ this: SlaveParserBase => //写入 SM或寄存器空间 val addrw = Reg(UInt(15.W)) + val logicAddrwNext = Wire( UInt(30.W) ) + val logicAddrw = RegNext(logicAddrwNext) val isWRReg = (addrw(14,11) === "b0000".U) - val isWRSM0 = (addrw(14,11) === "b0001".U) - val isWRSM2 = (addrw(14,11) === "b0011".U) - val isWRSM4 = (addrw(14,11) === "b0101".U) - val isWRSM6 = (addrw(14,11) === "b0111".U) + val isWRSM0 = (addrw(14,11) === "b0001".U) + val isWRSM2 = (addrw(14,11) === "b0011".U) + val isWRSM4 = (addrw(14,11) === "b0101".U) + val isWRSM6 = (addrw(14,11) === "b0111".U) val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(0).devIndex === localDevIndex)) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(1).devIndex === localDevIndex)) | + ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || downSubMsgInfo(0).isLgcIndex) ) | + ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || downSubMsgInfo(1).isLgcIndex) ) | ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) - when( downRecParser.io.subMsgReq.fire & ( - downRecParser.io.subMsgReq.bits.devIndex === localDevIndex | - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR - ) - ){ - addrw := downRecParser.io.subMsgReq.bits.address - } .elsewhen( isWrite & downRecParser.io.data.fire ){ - addrw := addrw + 1.U + val downTransLenCnt = RegInit(0.U) + + val isDownLgcAddrwAcquireTrans = //是否触发地址转换 + (downTransLenCnt === 0.U) & ( (0 until 8).map{ i => + sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) + }.reduce(_|_)) + + val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).pAddr + } + ) + + val acquireDownTransLen = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).length + } + ) + + when( isDownLgcAddrwAcquireTrans ){ //装填计数器 + downTransLenCnt := acquireDownTransLen + } .elsewhen( downRecParser.io.data.fire & downTransLenCnt =/= 0.U){ + downTransLenCnt := downTransLenCnt - 1.U } + //组合逻辑 + when( downRecParser.io.subMsgReq.fire & ( + (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex + )){//组合逻辑 + logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) + } .elsewhen( isWrite & downRecParser.io.data.fire ){//组合逻辑 + logicAddrwNext := logicAddrw + 1.U + } .otherwise{//组合逻辑 + logicAddrwNext := logicAddrw + } + + + when( downRecParser.io.subMsgReq.fire ){ //子包头装填 + when( + ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ){ //常规寻址 + addrw := downRecParser.io.subMsgReq.bits.address + } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ //逻辑寻址 + addrw := acquireDownPhyAddrw + } + } .elsewhen( isWrite & downRecParser.io.data.fire ){ + when( + ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ){ + addrw := addrw + 1.U + } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ + addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U ) + } + } + + + io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire io.lvds.dataw := downRecParser.io.data.bits @@ -453,10 +521,6 @@ trait SlaveParserRW{ this: SlaveParserBase => - // val SUBMSG_OPERATOR_BOARDREAD = "hd".U - // val SUBMSG_OPERATOR_BOARDWRITE = "he".U - // val SUBMSG_OPERATOR_BOARDRDWR = "hf".U - //上行接收 when( upRecParser.io.subMsgReq.fire ){ @@ -487,14 +551,55 @@ trait SlaveParserRW{ this: SlaveParserBase => //读出uSM val isRead = ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || upSubMsgInfo(0).isLgcIndex)) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || upSubMsgInfo(1).isLgcIndex)) | (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ) ) val addrr = Reg(UInt(15.W)) + val logicAddrrNext = Wire( UInt(30.W) ) + val logicAddrr = RegNext(logicAddrrNext) + + val upTransLenCnt = RegInit(0.U) + + val isUpLgcAddrwAcquireTrans = //是否触发地址转换 + (upTransLenCnt === 0.U) & ( (0 until 8).map{ i => + sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) + }.reduce(_|_)) + + val acquireUpPhyAddrw = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).pAddr + } + ) + + val acquireUpTransLen = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).length + } + ) + + when( isUpLgcAddrwAcquireTrans ){ //装填计数器 + upTransLenCnt := acquireUpTransLen + } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){ + upTransLenCnt := upTransLenCnt - 1.U + } + + //组合逻辑 + when( upRecParser.io.subMsgReq.fire & ( + (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex + )){//组合逻辑 + logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) + } .elsewhen( isRead & upRecParser.io.data.fire ){//组合逻辑 + logicAddrrNext := logicAddrw + 1.U + } .otherwise{//组合逻辑 + logicAddrrNext := logicAddrr + } + val isRDReg = addrr(14,11) === "b0000".U val isRDSM1 = addrr(14,11) === "b0010".U @@ -505,15 +610,24 @@ trait SlaveParserRW{ this: SlaveParserBase => val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) | upRecParser.io.data.fire ) - when( upRecParser.io.subMsgReq.fire & ( - upRecParser.io.subMsgReq.bits.devIndex === localDevIndex | - upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | - upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR - ) - ){ - addrr := upRecParser.io.subMsgReq.bits.address + when( upRecParser.io.subMsgReq.fire){ + when( + ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + ){ + addrr := upRecParser.io.subMsgReq.bits.address + } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + addrr := acquireUpPhyAddrw + } } .elsewhen( isLvdsEnR ){ - addrr := addrr + 1.U + when( + ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + ){ + addrr := addrr + 1.U + } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrwAcquireTrans, acquireUpPhyAddrw, 0.U), addrr + 1.U ) + } } val upStreamData = Mux1H(Seq( @@ -529,7 +643,7 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( - ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex, upStreamData, + ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | upSubMsgInfo(0).isLgcIndex), upStreamData, Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) ) @@ -544,7 +658,7 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.bits := Mux( - ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex, upStreamData, + ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | upSubMsgInfo(1).isLgcIndex), upStreamData, Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) From 1412f81a14af9f2cad80153982ea5c3e266fec83 Mon Sep 17 00:00:00 2001 From: bacon Date: Tue, 17 Jun 2025 19:40:25 +0800 Subject: [PATCH 04/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0ebmmu=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 16 +++++- tb/shinTest/gen_pkt.py | 112 ++++++++++++++++++++++++++++++++++++- 2 files changed, 123 insertions(+), 5 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 490b9a4..63f0cce 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -18,8 +18,8 @@ `define ENABLE_SYNC_TEST `define ENABLE_SYNC_SIG0_TEST -`define ENABLE_SYNC_SIG1_TEST -`define ENABLE_RESET_TEST +//`define ENABLE_SYNC_SIG1_TEST +//`define ENABLE_RESET_TEST module ShinTopSpiTb( @@ -1294,7 +1294,19 @@ initial begin */ end `endif + begin:RESET_SYSTEM_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例：EBMMU测试"); + + `include "ebmmu_settings.vh" + + `include "ebmmu_read.vh" + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end #1000000 diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index ba6b18f..1cc00b1 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -725,7 +725,7 @@ if __name__ == '__main__': data[19] = '''(_temp_time >> 24) & 8'hff''' data[24] = 0x00 #地址0x138, sync周期 4B - data[25] = 0x04 #地址0x139 + data[25] = 0x04 #地址0x139genPkt.addBeforeExc( data[28] = 0x0 #sync1偏移 data[29] = 0x0 @@ -844,7 +844,113 @@ if __name__ == '__main__': - - + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x00 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0200, 0x1, 10, data) + + + data = [0,] * 30 + data[0] = 0x0a + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x0200, 0x1, 10, data) + + + data = [0,] * 30 + + data[0] = 0x14 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0200, 0x1, 10, data) + + data = [0,] * 30 + + data[0] = 0x1e + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x02 + + data[6] = 0x0a + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x0200, 0x1, 10, data) + + + gen_file_def = "ebmmu_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 40 + + genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 40, data) + + gen_file_def = "ebmmu_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + From 773a15400334925417c9d78e9068fab4152eb1ec Mon Sep 17 00:00:00 2001 From: bacon Date: Tue, 17 Jun 2025 19:46:44 +0800 Subject: [PATCH 05/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0ebmmu=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 301bf87..d56b06b 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -10,11 +10,11 @@ //`define ENABLE_EXCHG_DATA_SEQ0_TEST //`define ENABLE_EXCHG_DATA_SEQ1_TEST //`define ENABLE_EXCHG_DATA_SEQ2_TEST -`define ENABLE_EXCHG_DATA_SEQ3_TEST +//`define ENABLE_EXCHG_DATA_SEQ3_TEST //`define ENABLE_BC_R_TEST //`define ENABLE_BC_W_TEST -`define ENABLE_BC_RW_TEST +//`define ENABLE_BC_RW_TEST `define ENABLE_SYNC_TEST `define ENABLE_SYNC_SIG0_TEST From 1579f4163a7586b14689f48c5a95cc2eed9037fd Mon Sep 17 00:00:00 2001 From: bacon Date: Tue, 17 Jun 2025 22:52:10 +0800 Subject: [PATCH 06/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=BB=A3=E7=A0=81?= =?UTF-8?q?=E9=87=87=E7=94=A8=E9=A1=BA=E5=BA=8F=E5=9C=B0=E5=9D=80=E8=AF=BB?= =?UTF-8?q?=E5=8F=96ebmmu=E7=9A=84=E9=85=8D=E7=BD=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 5 ++++- tb/shinTest/gen_pkt.py | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index d56b06b..039fb26 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -1295,7 +1295,8 @@ initial begin end `endif - begin:RESET_SYSTEM_TEST + + begin:EBMMU_TEST _t_start = $realtime; #1000 @@ -1303,6 +1304,8 @@ initial begin `include "ebmmu_settings.vh" + `include "ebmmu_seq_read.vh" + `include "ebmmu_read.vh" _t_end = $realtime; diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 1cc00b1..158bd30 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -931,6 +931,29 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + #------------------------------------------------------------------------- + #>>>>>>读取EB-MMU的设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 40 + + genPkt.addSubPkt(0x01, 0, 0x0200, 0x0, 10, data) + genPkt.addSubPkt(0x02, 0, 0x0200, 0x0, 10, data) + genPkt.addSubPkt(0x03, 0, 0x0200, 0x0, 10, data) + genPkt.addSubPkt(0x04, 0, 0x0200, 0x0, 10, data) + + gen_file_def = "ebmmu_seq_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + #------------------------------------------------------------------------- #>>>>>>设置EB-MMU From 7c6056e047370283b51f6ce45b01cf6ac09ab870 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 18 Jun 2025 15:31:28 +0800 Subject: [PATCH 07/41] =?UTF-8?q?=E9=80=BB=E8=BE=91=E5=9C=B0=E5=9D=80?= =?UTF-8?q?=E8=AF=BB=E8=BD=AC=E6=8D=A2=E4=BF=AE=E5=A4=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 40 +++++++++++-------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 23c08b1..6d5b74e 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -428,15 +428,15 @@ trait SlaveParserRW{ this: SlaveParserBase => val isWRSM4 = (addrw(14,11) === "b0101".U) val isWRSM6 = (addrw(14,11) === "b0111".U) + val downTransLenCnt = RegInit(0.U) val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || downSubMsgInfo(0).isLgcIndex) ) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || downSubMsgInfo(1).isLgcIndex) ) | + ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || ( downSubMsgInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | + ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || ( downSubMsgInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) - val downTransLenCnt = RegInit(0.U) val isDownLgcAddrwAcquireTrans = //是否触发地址转换 (downTransLenCnt === 0.U) & ( (0 until 8).map{ i => @@ -468,7 +468,10 @@ trait SlaveParserRW{ this: SlaveParserBase => (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex )){//组合逻辑 logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) - } .elsewhen( isWrite & downRecParser.io.data.fire ){//组合逻辑 + } .elsewhen( downRecParser.io.data.fire & ( + ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(0).isLgcIndex ) | + ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(1).isLgcIndex ) + )){//组合逻辑 logicAddrwNext := logicAddrw + 1.U } .otherwise{//组合逻辑 logicAddrwNext := logicAddrw @@ -547,12 +550,13 @@ trait SlaveParserRW{ this: SlaveParserBase => + val upTransLenCnt = RegInit(0.U) //读出uSM val isRead = ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || upSubMsgInfo(0).isLgcIndex)) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || upSubMsgInfo(1).isLgcIndex)) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) | (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ) @@ -562,28 +566,27 @@ trait SlaveParserRW{ this: SlaveParserBase => val logicAddrrNext = Wire( UInt(30.W) ) val logicAddrr = RegNext(logicAddrrNext) - val upTransLenCnt = RegInit(0.U) - val isUpLgcAddrwAcquireTrans = //是否触发地址转换 + val isUpLgcAddrrAcquireTrans = //是否触发地址转换 (upTransLenCnt === 0.U) & ( (0 until 8).map{ i => - sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) + sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr) }.reduce(_|_)) - val acquireUpPhyAddrw = Mux1H( //选择一个ebmmu + val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu (0 until 8).map{ i => - (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) -> sReg.ebmmu(i).pAddr } ) val acquireUpTransLen = Mux1H( //选择一个ebmmu (0 until 8).map{ i => - (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) -> sReg.ebmmu(i).length } ) - when( isUpLgcAddrwAcquireTrans ){ //装填计数器 + when( isUpLgcAddrrAcquireTrans ){ //装填计数器 upTransLenCnt := acquireUpTransLen } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){ upTransLenCnt := upTransLenCnt - 1.U @@ -594,8 +597,11 @@ trait SlaveParserRW{ this: SlaveParserBase => (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex )){//组合逻辑 logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) - } .elsewhen( isRead & upRecParser.io.data.fire ){//组合逻辑 - logicAddrrNext := logicAddrw + 1.U + } .elsewhen( upRecParser.io.data.fire & ( + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex ) + ) ){//组合逻辑 + logicAddrrNext := logicAddrr + 1.U } .otherwise{//组合逻辑 logicAddrrNext := logicAddrr } @@ -617,7 +623,7 @@ trait SlaveParserRW{ this: SlaveParserBase => ){ addrr := upRecParser.io.subMsgReq.bits.address } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - addrr := acquireUpPhyAddrw + addrr := acquireUpPhyAddrr } } .elsewhen( isLvdsEnR ){ when( @@ -626,7 +632,7 @@ trait SlaveParserRW{ this: SlaveParserBase => ){ addrr := addrr + 1.U } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrwAcquireTrans, acquireUpPhyAddrw, 0.U), addrr + 1.U ) + addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrrAcquireTrans, acquireUpPhyAddrr, 0.U), addrr + 1.U ) } } From 63be2890e44f6d35b3aed7cd696c6776de878183 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 18 Jun 2025 16:45:44 +0800 Subject: [PATCH 08/41] =?UTF-8?q?ebmmu=E8=AF=BB=E6=93=8D=E4=BD=9C=E4=BF=AE?= =?UTF-8?q?=E5=A4=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 2 +- src/main/scala/backBoard/shin/SlaveParser.scala | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 7cee3a9..e332f12 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -768,7 +768,7 @@ trait InterfaceLVDSop{ this: InterfaceBase => ) sReg.ebmmu(i).op := - RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) + RegEnable( io.lvds.dataw, false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) sReg.ebmmu(i).isEnable := RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) ) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 6d5b74e..5c39310 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -625,7 +625,7 @@ trait SlaveParserRW{ this: SlaveParserBase => } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ addrr := acquireUpPhyAddrr } - } .elsewhen( isLvdsEnR ){ + } .elsewhen( upRecParser.io.data.fire ){ when( ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) @@ -649,7 +649,7 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( - ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | upSubMsgInfo(0).isLgcIndex), upStreamData, + ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) ) @@ -664,7 +664,7 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.bits := Mux( - ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | upSubMsgInfo(1).isLgcIndex), upStreamData, + ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) From 47ff36aa693df2907ffa1147e855c874db45db63 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 18 Jun 2025 18:53:47 +0800 Subject: [PATCH 09/41] =?UTF-8?q?=E5=9F=BA=E6=9C=AC=E5=8F=AF=E7=94=A8?= =?UTF-8?q?=EF=BC=8C=E9=9C=80=E8=A6=81=E4=BC=98=E5=8C=96?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 39 ++++++++++++------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 5c39310..61bd9bb 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -552,15 +552,6 @@ trait SlaveParserRW{ this: SlaveParserBase => val upTransLenCnt = RegInit(0.U) - //读出uSM - val isRead = - ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) | - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) - ) - ) val addrr = Reg(UInt(15.W)) val logicAddrrNext = Wire( UInt(30.W) ) @@ -613,8 +604,24 @@ trait SlaveParserRW{ this: SlaveParserBase => val isRDSM5 = addrr(14,11) === "b0110".U val isRDSM7 = addrr(14,11) === "b1000".U - val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) | - upRecParser.io.data.fire ) + + val isSeqRead = + ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) )) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) + ) + ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire ) + + val isLgcRead = + ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) + ) + ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire ) + + val isLvdsEnR = isSeqRead | isLgcRead when( upRecParser.io.subMsgReq.fire){ when( @@ -625,14 +632,20 @@ trait SlaveParserRW{ this: SlaveParserBase => } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ addrr := acquireUpPhyAddrr } - } .elsewhen( upRecParser.io.data.fire ){ + } .elsewhen( isUpLgcAddrrAcquireTrans ){ + when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + addrr := acquireUpPhyAddrr + } + } + .elsewhen( isLvdsEnR ){ + assert(~isUpLgcAddrrAcquireTrans) when( ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ){ addrr := addrr + 1.U } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrrAcquireTrans, acquireUpPhyAddrr, 0.U), addrr + 1.U ) + addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) } } From 8149c48100c04b794da2071b17b1d04aa66930ce Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 19 Jun 2025 14:30:47 +0800 Subject: [PATCH 10/41] =?UTF-8?q?=E4=BB=A3=E7=A0=81=E9=80=BB=E8=BE=91?= =?UTF-8?q?=E4=BC=98=E5=8C=96=EF=BC=8C=E5=A2=9E=E5=BC=BA=E4=BF=9D=E6=8A=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 99 +++++++++++++------ 1 file changed, 69 insertions(+), 30 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 61bd9bb..d5bbfa8 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -577,9 +577,13 @@ trait SlaveParserRW{ this: SlaveParserBase => } ) - when( isUpLgcAddrrAcquireTrans ){ //装填计数器 + when( isUpLgcAddrrAcquireTrans & ( + (upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + )){ //装填计数器 upTransLenCnt := acquireUpTransLen - } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){ + } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){ upTransLenCnt := upTransLenCnt - 1.U } @@ -588,11 +592,15 @@ trait SlaveParserRW{ this: SlaveParserBase => (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex )){//组合逻辑 logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) - } .elsewhen( upRecParser.io.data.fire & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex ) - ) ){//组合逻辑 - logicAddrrNext := logicAddrr + 1.U + } .elsewhen( upRecParser.io.data.fire){ + when( + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex ) + ){//组合逻辑 + logicAddrrNext := logicAddrr + 1.U + } .otherwise{ + logicAddrrNext := 0.U + } } .otherwise{//组合逻辑 logicAddrrNext := logicAddrr } @@ -623,38 +631,69 @@ trait SlaveParserRW{ this: SlaveParserBase => val isLvdsEnR = isSeqRead | isLgcRead - when( upRecParser.io.subMsgReq.fire){ - when( - ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | - ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) - ){ + + + + + // when( upRecParser.io.subMsgReq.fire){ + // when( + // ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + // ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + // ){ + // addrr := upRecParser.io.subMsgReq.bits.address + // } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + // addrr := acquireUpPhyAddrr + // } + // } .elsewhen( isUpLgcAddrrAcquireTrans ){ + // when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + // addrr := acquireUpPhyAddrr + // } + // } + // .elsewhen( isLvdsEnR ){ + // assert(~isUpLgcAddrrAcquireTrans) + // when( + // ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + // ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + // ){ + // addrr := addrr + 1.U + // } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + // addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) + // } + // } + + when( + ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + ){ + when( upRecParser.io.subMsgReq.fire){ addrr := upRecParser.io.subMsgReq.bits.address - } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - addrr := acquireUpPhyAddrr + } .elsewhen(isLvdsEnR){ + addrr := addrr + 1.U } } .elsewhen( isUpLgcAddrrAcquireTrans ){ - when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + when( + (upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + ){ addrr := acquireUpPhyAddrr } - } - .elsewhen( isLvdsEnR ){ + } .elsewhen( isLvdsEnR & ( + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + )){ assert(~isUpLgcAddrrAcquireTrans) - when( - ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | - ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) - ){ - addrr := addrr + 1.U - } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) - } + addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) } + + val upStreamData = Mux1H(Seq( - isRDReg -> io.lvds.datar, - isRDSM1 -> io.sram_r(0).datar, - isRDSM3 -> io.sram_r(1).datar, - isRDSM5 -> io.sram_r(2).datar, - isRDSM7 -> io.sram_r(3).datar, + isRDReg -> io.lvds.datar, + isRDSM1 -> io.sram_r(0).datar, + isRDSM3 -> io.sram_r(1).datar, + isRDSM5 -> io.sram_r(2).datar, + isRDSM7 -> io.sram_r(3).datar, )) From 703169adff5378548bfee0b6de9d3b225c301097 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 19 Jun 2025 15:36:44 +0800 Subject: [PATCH 11/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0EBMMU=E7=9A=84=E6=96=B0?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 39 +++++++++-- tb/shinTest/gen_pkt.py | 137 +++++++++++++++++++++++++++++++++++-- 2 files changed, 167 insertions(+), 9 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 039fb26..3dccd9b 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -21,6 +21,10 @@ //`define ENABLE_SYNC_SIG1_TEST //`define ENABLE_RESET_TEST +`define ENABLE_EBMMU_TC1_TEST +`define ENABLE_EBMMU_TC2_TEST +`define ENABLE_EBMMU_TC3_TEST + module ShinTopSpiTb( ); @@ -1296,22 +1300,47 @@ initial begin end `endif - begin:EBMMU_TEST +`ifdef ENABLE_EBMMU_TC1_TEST + begin:EBMMU_TC1_TEST _t_start = $realtime; #1000 - $fdisplay(spidata_file, "\n\n测试用例：EBMMU测试"); + $fdisplay(spidata_file, "\n\n测试用例：EBMMU测试 1"); - `include "ebmmu_settings.vh" + `include "ebmmu_tc1_settings.vh" - `include "ebmmu_seq_read.vh" + `include "ebmmu_tc1_seq_read.vh" - `include "ebmmu_read.vh" + `include "ebmmu_tc1_read.vh" _t_end = $realtime; $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); end +`endif +`ifdef ENABLE_EBMMU_TC2_TEST + begin:EBMMU_TC2_TEST + _t_start = $realtime; + #1000 + + $fdisplay(spidata_file, "\n\n测试用例：EBMMU测试 2"); + + `include "ebmmu_tc2_settings.vh" + + `include "ebmmu_tc2_seq_read.vh" + + `include "ebmmu_tc2_read.vh" + + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end +`endif + + +`ifdef ENABLE_EBMMU_TC3_TEST + +`endif #1000000 $display("Testcase Finished! Time Out !!!"); diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 158bd30..0992fca 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -921,7 +921,7 @@ if __name__ == '__main__': genPkt.addSubPkt(0x4, 0, 0x0200, 0x1, 10, data) - gen_file_def = "ebmmu_settings" + gen_file_def = "ebmmu_tc1_settings" sm_idx = 0 genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) @@ -944,7 +944,7 @@ if __name__ == '__main__': genPkt.addSubPkt(0x03, 0, 0x0200, 0x0, 10, data) genPkt.addSubPkt(0x04, 0, 0x0200, 0x0, 10, data) - gen_file_def = "ebmmu_seq_read" + gen_file_def = "ebmmu_tc1_seq_read" sm_idx = 0 genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) @@ -956,7 +956,7 @@ if __name__ == '__main__': #------------------------------------------------------------------------- - #>>>>>>设置EB-MMU + #>>>>>>用EB-MMU方式读取EB-MMU设置 genPkt.clean() genPkt.setPktType(0) @@ -965,7 +965,7 @@ if __name__ == '__main__': genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 40, data) - gen_file_def = "ebmmu_read" + gen_file_def = "ebmmu_tc1_read" sm_idx = 0 genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) @@ -975,5 +975,134 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x00 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0f + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x020a, 0x1, 10, data) + data = [0,] * 30 + data[0] = 0x10 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0f + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x020a, 0x1, 10, data) + + + data = [0,] * 30 + + data[0] = 0x20 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0f + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x020a, 0x1, 10, data) + + data = [0,] * 30 + + data[0] = 0x30 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x20 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x0f + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x020a, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc2_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>读取数据 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 40 + + genPkt.addSubPkt(0x01, 0, 0x0000, 0x0, 16, data) + genPkt.addSubPkt(0x02, 0, 0x0000, 0x0, 16, data) + genPkt.addSubPkt(0x03, 0, 0x0000, 0x0, 16, data) + genPkt.addSubPkt(0x04, 0, 0x0000, 0x0, 16, data) + + gen_file_def = "ebmmu_tc2_seq_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 100 + + genPkt.addSubPkt(0x2000, 2, 0x0000, 0x0, 0x40, data) + + gen_file_def = "ebmmu_tc2_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + From aa910382d0d71bc5c0a620dccbf9dcecfb5795f7 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 19 Jun 2025 17:55:23 +0800 Subject: [PATCH 12/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0ebmmu=E7=9A=84=E6=B5=8B?= =?UTF-8?q?=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 13 +++++ tb/shinTest/gen_pkt.py | 117 +++++++++++++++++++++++++++++++++++-- 2 files changed, 126 insertions(+), 4 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 3dccd9b..61aa2dc 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -1339,7 +1339,20 @@ initial begin `ifdef ENABLE_EBMMU_TC3_TEST + begin:EBMMU_TC3_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例：EBMMU测试 3"); + + `include "ebmmu_tc3_settings.vh" + + `include "ebmmu_tc3_read.vh" + + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end `endif #1000000 diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 0992fca..d760a63 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -991,7 +991,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x0f + data[6] = 0x10 data[7] = 0x00 data[8] = 0x01 @@ -1009,7 +1009,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x0f + data[6] = 0x10 data[7] = 0x00 data[8] = 0x01 @@ -1027,7 +1027,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x0f + data[6] = 0x10 data[7] = 0x00 data[8] = 0x01 @@ -1044,7 +1044,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x0f + data[6] = 0x10 data[7] = 0x00 data[8] = 0x01 @@ -1106,3 +1106,112 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x1e + 0xa + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0214, 0x1, 10, data) + + + data = [0,] * 30 + data[0] = 0x1e + 0xa + 0x10 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x0214, 0x1, 10, data) + + + data = [0,] * 30 + + data[0] = 0x1e + 0xa + 0x10 + 0x10 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0214, 0x1, 10, data) + + data = [0,] * 30 + + data[0] = 0x1e + 0xa + 0x10 + 0x10 + 0x10 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x00 + + data[6] = 0x10 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x0214, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc3_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 150 + + genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 0x40 + 0x28, data) + + gen_file_def = "ebmmu_tc3_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) From c45f78ed1281ed0b8392c085afef0bbb7df5c432 Mon Sep 17 00:00:00 2001 From: bacon Date: Fri, 20 Jun 2025 00:07:18 +0800 Subject: [PATCH 13/41] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index d760a63..411eaa5 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1124,7 +1124,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x10 + data[6] = 0x0c data[7] = 0x00 data[8] = 0x01 @@ -1134,7 +1134,7 @@ if __name__ == '__main__': data = [0,] * 30 - data[0] = 0x1e + 0xa + 0x10 + data[0] = 0x1e + 0xa + 0x0c data[1] = 0x00 data[2] = 0x00 data[3] = 0x10 @@ -1142,7 +1142,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x10 + data[6] = 0x0c data[7] = 0x00 data[8] = 0x01 @@ -1152,7 +1152,7 @@ if __name__ == '__main__': data = [0,] * 30 - data[0] = 0x1e + 0xa + 0x10 + 0x10 + data[0] = 0x1e + 0xa + 0x0c + 0x0c data[1] = 0x00 data[2] = 0x00 data[3] = 0x10 @@ -1160,7 +1160,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x10 + data[6] = 0x0c data[7] = 0x00 data[8] = 0x01 @@ -1169,7 +1169,7 @@ if __name__ == '__main__': data = [0,] * 30 - data[0] = 0x1e + 0xa + 0x10 + 0x10 + 0x10 + data[0] = 0x1e + 0xa + 0x0c + 0x0c + 0x0c data[1] = 0x00 data[2] = 0x00 data[3] = 0x10 @@ -1177,7 +1177,7 @@ if __name__ == '__main__': data[4] = 0x00 data[5] = 0x00 - data[6] = 0x10 + data[6] = 0x0c data[7] = 0x00 data[8] = 0x01 @@ -1204,7 +1204,7 @@ if __name__ == '__main__': #subPkt参数：索引、索引类型、地址、命令、长度、数据 data = [0,] * 150 - genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 0x40 + 0x28, data) + genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 0x0c * 4 + 0x28, data) gen_file_def = "ebmmu_tc3_read" sm_idx = 0 From cab7a7725788e3da4bfe572c27ec93acf1e9d736 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 20 Jun 2025 11:09:04 +0800 Subject: [PATCH 14/41] =?UTF-8?q?=E4=BF=AE=E5=A4=8Debmmu=20op=E7=9A=84?= =?UTF-8?q?=E4=BD=8D=E5=AE=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index e332f12..c9244e9 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -768,7 +768,7 @@ trait InterfaceLVDSop{ this: InterfaceBase => ) sReg.ebmmu(i).op := - RegEnable( io.lvds.dataw, false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) + RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) ) sReg.ebmmu(i).isEnable := RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) ) From a4594f77de0444a45a5f3652282f8a645e14e349 Mon Sep 17 00:00:00 2001 From: bacon Date: Fri, 20 Jun 2025 15:08:48 +0800 Subject: [PATCH 15/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E6=96=B0=E7=9A=84?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B,=E6=93=8D=E4=BD=9CSM?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 60 +++++++++++++++++++- tb/shinTest/gen_pkt.py | 109 +++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+), 3 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 61aa2dc..7cff8eb 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -21,9 +21,10 @@ //`define ENABLE_SYNC_SIG1_TEST //`define ENABLE_RESET_TEST -`define ENABLE_EBMMU_TC1_TEST -`define ENABLE_EBMMU_TC2_TEST -`define ENABLE_EBMMU_TC3_TEST +//`define ENABLE_EBMMU_TC1_TEST +//`define ENABLE_EBMMU_TC2_TEST +//`define ENABLE_EBMMU_TC3_TEST +`define ENABLE_EBMMU_TC4_TEST module ShinTopSpiTb( @@ -1355,6 +1356,59 @@ initial begin end `endif +`ifdef ENABLE_EBMMU_TC4_TEST + begin:EBMMU_TC4_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用4"); + $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); + + txBuf[3] = 8'h80; + txBuf[4] = 8'h00; + spi_trans((16'h0306), (`SPI_WRITE), (2), (`IF_IDX(1)) );//dev1_sm1 + + txBuf[3] = 8'h98; + txBuf[4] = 8'h00; + spi_trans((16'h030e), (`SPI_WRITE), (2), (`IF_IDX(2)) );//dev2_sm3 + + txBuf[3] = 8'h81; + txBuf[4] = 8'h00; + spi_trans((16'h0316), (`SPI_WRITE), (2), (`IF_IDX(3)) );//dev2_sm3 + + txBuf[3] = 8'h8c; + txBuf[4] = 8'h00; + spi_trans((16'h031e), (`SPI_WRITE), (2), (`IF_IDX(4)) );//dev2_sm3 + + + for (integer i=0; i < 128; i++) begin + txBuf[i + 3] = i + 1; + end + spi_trans( (16'h1000), (`SPI_WRITE), (128), (`IF_IDX(1)) ); + + for (integer i=0; i < 152; i++) begin + txBuf[i + 3] = i + 2; + end + spi_trans( (16'h2000), (`SPI_WRITE), (152), (`IF_IDX(2)) ); + + for (integer i=0; i < 129; i++) begin + txBuf[i + 3] = i + 3; + end + spi_trans( (16'h3000), (`SPI_WRITE), (129), (`IF_IDX(3)) ); + + for (integer i=0; i < 140; i++) begin + txBuf[i + 3] = i + 4; + end + spi_trans( (16'h4000), (`SPI_WRITE), (140), (`IF_IDX(4)) ); + + `include "ebmmu_tc4_settings.vh" + + `include "ebmmu_tc4_read.vh" + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end +`endif + #1000000 $display("Testcase Finished! Time Out !!!"); $fclose(spidata_file); diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 411eaa5..566461e 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1215,3 +1215,112 @@ if __name__ == '__main__': +genReadAckPktCode(gen_file_def, sm_idx)) genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + data[0] = 0x58 #0x1e + 0xa + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x10 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x021e, 0x1, 10, data) + + + data = [0,] * 30 + data[0] = 0x58 + 0x80 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x20 + + data[6] = 0x98 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x021e, 0x1, 10, data) + + + data = [0,] * 30 + + data[0] = 0x58 + 0x80 + 0x98 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x30 + + data[6] = 0x81 + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x021e, 0x1, 10, data) + + data = [0,] * 30 + + data[0] = 0x58 + 0x80 + 0x98 + 0x81 + data[1] = 0x00 + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x40 + + data[6] = 0x8c + data[7] = 0x00 + + data[8] = 0x01 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x021e, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc4_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 550 + + genPkt.addSubPkt(0x1000, 2, 0x0058, 0x0, 0x80+0x98+0x81+0x8c, data) + + gen_file_def = "ebmmu_tc4_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + From d79e7120566c4a22968f464312aa7794eef65cbb Mon Sep 17 00:00:00 2001 From: bacon Date: Fri, 20 Jun 2025 19:10:24 +0800 Subject: [PATCH 16/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=BB=A3=E7=A0=81,?= =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B=E7=9A=84?= =?UTF-8?q?=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 566461e..a54a8c7 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1242,8 +1242,9 @@ if __name__ == '__main__': data = [0,] * 30 - data[0] = 0x58 + 0x80 - data[1] = 0x00 + addr = 0x58 + 0x80 + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff data[2] = 0x00 data[3] = 0x10 @@ -1259,9 +1260,9 @@ if __name__ == '__main__': data = [0,] * 30 - - data[0] = 0x58 + 0x80 + 0x98 - data[1] = 0x00 + addr = 0x58 + 0x80 + 0x98 + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff data[2] = 0x00 data[3] = 0x10 @@ -1277,8 +1278,9 @@ if __name__ == '__main__': data = [0,] * 30 - data[0] = 0x58 + 0x80 + 0x98 + 0x81 - data[1] = 0x00 + addr = 0x58 + 0x80 + 0x98 + 0x81 + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff data[2] = 0x00 data[3] = 0x10 From a7f27f5bf0cd2bb846481f98c5b56d9e448887b4 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 24 Jun 2025 10:23:46 +0800 Subject: [PATCH 17/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=AD=90=E6=8A=A5?= =?UTF-8?q?=E6=96=87=E5=B0=BE=EF=BC=8C=E6=94=BE=E7=BD=AEworkcnt?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 456 ++++++++++-------- .../scala/backBoard/shin/SlaveRecParser.scala | 109 +++-- .../scala/backBoard/shin/SlaveSendGen.scala | 87 ++-- 3 files changed, 372 insertions(+), 280 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index d5bbfa8..d611480 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -16,12 +16,15 @@ class SubMsgHeader extends Bundle{ val address = UInt(16.W) //子报文地址 val operator = UInt(4.W) //子报文命令类型 val length = UInt(12.W) //子报文负载长度 - val workCnt = UInt(16.W) //子报文工作计数 + def isSeqIndex = style === 0.U def isLgcIndex = style === 2.U } +class SubMsgTail extends Bundle{ + val workCnt = UInt(16.W) //子报文工作计数 +} // class ShareSRAMIO extends Bundle{ @@ -98,11 +101,12 @@ abstract class SlaveParserBase extends Module{ val STATE_IDLE = 0.U //空闲 val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 - val STATE_SUBMSG_HEADER = 2.U //子报文头 + val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型 val STATE_PAYLOAD_DATA = 3.U //子报文数据 - val STATE_CRC = 4.U //CRC校验 - val STATE_ERROR = 5.U // - val STATE_WAIT = 6.U + val STATE_SUBMSG_TAIL = 4.U + val STATE_CRC = 5.U //CRC校验 + val STATE_ERROR = 6.U // + val STATE_WAIT = 7.U @@ -115,9 +119,7 @@ abstract class SlaveParserBase extends Module{ val isAckProbe = RegInit(false.B) val isLastDevice: Bool = RegInit(true.B) - // val isDevOnLeft = RegInit(0.U(2.W)); io.isDevOnLeft := isDevOnLeft - // val isDevOnLeftModify = RegInit(false.B); io.isDevOnLeftModify := isDevOnLeftModify - // val indexOfLeftDev = RegInit(0.U(14.W)); io.indexOfLeftDev := indexOfLeftDev + io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U ) val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev @@ -172,18 +174,21 @@ abstract class SlaveParserBase extends Module{ //////////////////////////////////////// //子报文 - val isDownSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } - val isUpSubMsgValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } - + val isDownSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } + val isUpSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } + val isDownSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } + val isUpSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) } //接收子报文 - val downSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头 - val upSubMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } + val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头 + val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } + val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头 + val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载 @@ -195,37 +200,42 @@ abstract class SlaveParserBase extends Module{ //下行接收 - when( downRecParser.io.subMsgReq.fire ){ + when( downRecParser.io.subMsgHeadReq.fire ){ when( isDownRecPing ){ - downSubMsgInfo(0).devIndex := downRecParser.io.subMsgReq.bits.devIndex - downSubMsgInfo(0).style := downRecParser.io.subMsgReq.bits.style - downSubMsgInfo(0).address := downRecParser.io.subMsgReq.bits.address - downSubMsgInfo(0).operator := downRecParser.io.subMsgReq.bits.operator - downSubMsgInfo(0).length := downRecParser.io.subMsgReq.bits.length - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt - downSubMsgInfo(0).source := 0.U + downSubMsgHeadInfo(0).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex + downSubMsgHeadInfo(0).style := downRecParser.io.subMsgHeadReq.bits.style + downSubMsgHeadInfo(0).address := downRecParser.io.subMsgHeadReq.bits.address + downSubMsgHeadInfo(0).operator := downRecParser.io.subMsgHeadReq.bits.operator + downSubMsgHeadInfo(0).length := downRecParser.io.subMsgHeadReq.bits.length + downSubMsgHeadInfo(0).source := 0.U } .otherwise{ //pong - downSubMsgInfo(1).devIndex := downRecParser.io.subMsgReq.bits.devIndex - downSubMsgInfo(1).style := downRecParser.io.subMsgReq.bits.style - downSubMsgInfo(1).address := downRecParser.io.subMsgReq.bits.address - downSubMsgInfo(1).operator := downRecParser.io.subMsgReq.bits.operator - downSubMsgInfo(1).length := downRecParser.io.subMsgReq.bits.length - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt - downSubMsgInfo(1).source := 1.U + downSubMsgHeadInfo(1).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex + downSubMsgHeadInfo(1).style := downRecParser.io.subMsgHeadReq.bits.style + downSubMsgHeadInfo(1).address := downRecParser.io.subMsgHeadReq.bits.address + downSubMsgHeadInfo(1).operator := downRecParser.io.subMsgHeadReq.bits.operator + downSubMsgHeadInfo(1).length := downRecParser.io.subMsgHeadReq.bits.length + downSubMsgHeadInfo(1).source := 1.U + } + } + + when( downRecParser.io.subMsgTailReq.fire ){ + when( isDownRecPing ){ + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + } .otherwise{ //pong + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt } } - when( ~isDownRecPing ){ //req fire 后 已经反相 + when( isDownRecPing ){ //req fire 后 downRecFifo(0).io.enq.valid := downRecParser.io.data.valid downRecFifo(0).io.enq.bits := downRecParser.io.data.bits downRecParser.io.data.ready := downRecFifo(0).io.enq.ready downRecFifo(1).io.enq.valid := false.B downRecFifo(1).io.enq.bits := 0.U - } .otherwise{ downRecFifo(0).io.enq.valid := false.B downRecFifo(0).io.enq.bits := 0.U @@ -240,27 +250,31 @@ abstract class SlaveParserBase extends Module{ //上行接收 - when( upRecParser.io.subMsgReq.fire ){ + when( upRecParser.io.subMsgHeadReq.fire ){ when( isUpRecPing ){ - upSubMsgInfo(0).devIndex := upRecParser.io.subMsgReq.bits.devIndex - upSubMsgInfo(0).style := upRecParser.io.subMsgReq.bits.style - upSubMsgInfo(0).address := upRecParser.io.subMsgReq.bits.address - upSubMsgInfo(0).operator := upRecParser.io.subMsgReq.bits.operator - upSubMsgInfo(0).length := upRecParser.io.subMsgReq.bits.length - upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt - upSubMsgInfo(0).source := 0.U + upSubMsgHeadInfo(0).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex + upSubMsgHeadInfo(0).style := upRecParser.io.subMsgHeadReq.bits.style + upSubMsgHeadInfo(0).address := upRecParser.io.subMsgHeadReq.bits.address + upSubMsgHeadInfo(0).operator := upRecParser.io.subMsgHeadReq.bits.operator + upSubMsgHeadInfo(0).length := upRecParser.io.subMsgHeadReq.bits.length + upSubMsgHeadInfo(0).source := 0.U } .otherwise{ - upSubMsgInfo(1).devIndex := upRecParser.io.subMsgReq.bits.devIndex - upSubMsgInfo(1).style := upRecParser.io.subMsgReq.bits.style - upSubMsgInfo(1).address := upRecParser.io.subMsgReq.bits.address - upSubMsgInfo(1).operator := upRecParser.io.subMsgReq.bits.operator - upSubMsgInfo(1).length := upRecParser.io.subMsgReq.bits.length - upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt - upSubMsgInfo(1).source := 1.U + upSubMsgHeadInfo(1).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex + upSubMsgHeadInfo(1).style := upRecParser.io.subMsgHeadReq.bits.style + upSubMsgHeadInfo(1).address := upRecParser.io.subMsgHeadReq.bits.address + upSubMsgHeadInfo(1).operator := upRecParser.io.subMsgHeadReq.bits.operator + upSubMsgHeadInfo(1).length := upRecParser.io.subMsgHeadReq.bits.length + upSubMsgHeadInfo(1).source := 1.U } } - + when( upRecParser.io.subMsgTailReq.fire ){ + when( isUpRecPing ){ + upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + } .otherwise{ + upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + } + } @@ -274,71 +288,106 @@ abstract class SlaveParserBase extends Module{ - downSendGen.io.subMsgReq.valid := - ( isDownSendPing & isDownSubMsgValid(0) ) | (~isDownSendPing & isDownSubMsgValid(1)) + downSendGen.io.subMsgHeadReq.valid := + ( isDownSendPing & isDownSubMsgHeadValid(0) ) | (~isDownSendPing & isDownSubMsgHeadValid(1)) - downSendGen.io.subMsgReq.bits := Mux( isDownSendPing, downSubMsgInfo(0), downSubMsgInfo(1) ) + downSendGen.io.subMsgHeadReq.bits := Mux( isDownSendPing, downSubMsgHeadInfo(0), downSubMsgHeadInfo(1) ) - when( downSendGen.io.subMsgReq.fire ){ //ready - isDownSendPing := ~isDownSendPing + downSendGen.io.subMsgTailReq.valid := + ( isDownSendPing & isDownSubMsgTailValid(0) ) | ( ~isDownSendPing & isDownSubMsgTailValid(1)) + + downSendGen.io.subMsgTailReq.bits := Mux( isDownSendPing, downSubMsgTailInfo(0), downSubMsgTailInfo(1) ) + + + + when( downSendGen.io.subMsgHeadReq.fire ){ //ready when( isDownSendPing ){ - assert( isDownSubMsgValid(0) ) - isDownSubMsgValid(0) := false.B + assert( isDownSubMsgHeadValid(0) ) + isDownSubMsgHeadValid(0) := false.B } .otherwise{ - assert( isDownSubMsgValid(1) ) - isDownSubMsgValid(1) := false.B + assert( isDownSubMsgHeadValid(1) ) + isDownSubMsgHeadValid(1) := false.B } - } .elsewhen( downRecParser.io.subMsgReq.fire ){ - isDownRecPing := ~isDownRecPing + } .elsewhen( downRecParser.io.subMsgHeadReq.fire ){ when( isDownRecPing ){ - assert( ~isDownSubMsgValid(0) ) - isDownSubMsgValid(0) := true.B + assert( ~isDownSubMsgHeadValid(0) ) + isDownSubMsgHeadValid(0) := true.B } .otherwise{ - assert( ~isDownSubMsgValid(1) ) - isDownSubMsgValid(1) := true.B + assert( ~isDownSubMsgHeadValid(1) ) + isDownSubMsgHeadValid(1) := true.B } } + when( downSendGen.io.subMsgTailReq.fire ){ + when( isDownSendPing ){ + assert( isDownSubMsgTailValid(0) ) + isDownSubMsgTailValid(0) := false.B + } .otherwise{ + assert( isDownSubMsgTailValid(1) ) + isDownSubMsgTailValid(1) := false.B + } + } .elsewhen( downRecParser.io.subMsgTailReq.fire ){ + when( isDownRecPing ){ + assert( ~isDownSubMsgTailValid(0) ) + isDownSubMsgTailValid(0) := true.B + } .otherwise{ + assert( ~isDownSubMsgTailValid(1) ) + isDownSubMsgTailValid(1) := true.B + } + } + + when( downSendGen.io.subMsgTailReq.fire ){ //ready + isDownSendPing := ~isDownSendPing + } .elsewhen( downRecParser.io.subMsgTailReq.fire ){ + isDownRecPing := ~isDownRecPing + } downRecFifo(0).io.deq <> downSendGen.io.data(0) downRecFifo(1).io.deq <> downSendGen.io.data(1) - downRecParser.io.resp := ( downRecParser.io.stateCurr === STATE_WAIT ) & (~isDownSubMsgValid(0) & ~isDownSubMsgValid(1)) - //子报文上行发送 - upSendGen.io.subMsgReq.valid := - ( isUpSendPing & isUpSubMsgValid(0) ) | - ( ~isUpSendPing & isUpSubMsgValid(1) ) + upSendGen.io.subMsgHeadReq.valid := + ( isUpSendPing & isUpSubMsgHeadValid(0) ) | + ( ~isUpSendPing & isUpSubMsgHeadValid(1) ) - upSendGen.io.subMsgReq.bits := Mux( isUpSendPing, upSubMsgInfo(0), upSubMsgInfo(1) ) + upSendGen.io.subMsgHeadReq.bits := Mux( isUpSendPing, upSubMsgHeadInfo(0), upSubMsgHeadInfo(1) ) - when( upSendGen.io.subMsgReq.fire ){ //ready - isUpSendPing := ~isUpSendPing + upSendGen.io.subMsgTailReq.valid := + ( isUpSendPing & isUpSubMsgTailValid(0) ) | + ( ~isUpSendPing & isUpSubMsgTailValid(1) ) + + upSendGen.io.subMsgTailReq.bits := Mux( isUpSendPing, upSubMsgTailInfo(0), upSubMsgTailInfo(1) ) + + when( upSendGen.io.subMsgHeadReq.fire ){ //ready when( isUpSendPing ){ - assert( isUpSubMsgValid(0) ) - isUpSubMsgValid(0) := false.B + assert( isUpSubMsgHeadValid(0) ) + isUpSubMsgHeadValid(0) := false.B } .otherwise{ - assert( isUpSubMsgValid(1) ) - isUpSubMsgValid(1) := false.B + assert( isUpSubMsgHeadValid(1) ) + isUpSubMsgHeadValid(1) := false.B } - }.elsewhen( upRecParser.io.subMsgReq.fire ){ - isUpRecPing := ~isUpRecPing + }.elsewhen( upRecParser.io.subMsgHeadReq.fire ){ when( isUpRecPing ){ - assert( ~isUpSubMsgValid(0) ) - isUpSubMsgValid(0) := true.B + assert( ~isUpSubMsgHeadValid(0) ) + isUpSubMsgHeadValid(0) := true.B } .otherwise{ - assert( ~isUpSubMsgValid(1) ) - isUpSubMsgValid(1) := true.B + assert( ~isUpSubMsgHeadValid(1) ) + isUpSubMsgHeadValid(1) := true.B } } + when( upSendGen.io.subMsgHeadReq.fire ){ //ready + isUpSendPing := ~isUpSendPing + }.elsewhen( upRecParser.io.subMsgHeadReq.fire ){ + isUpRecPing := ~isUpRecPing + } + upRecFifo(0).io.deq <> upSendGen.io.data(0) upRecFifo(1).io.deq <> upSendGen.io.data(1) - upRecParser.io.resp := ( upRecParser.io.stateCurr === STATE_WAIT ) & (~isUpSubMsgValid(0) & ~isUpSubMsgValid(1)) } @@ -357,22 +406,40 @@ abstract class SlaveParserBase extends Module{ trait SlaveParserIndex{ this: SlaveParserBase => - //下行接收 - when( downRecParser.io.subMsgReq.fire & - downRecParser.io.subMsgReq.bits.devIndex === 0.U & - downRecParser.io.subMsgReq.bits.style === 0.U & - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址 - localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U - indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U) - when( isDownRecPing ){ - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U - } .otherwise{ //pong - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + //下行接收 + when( downRecParser.io.subMsgTailReq.fire ){ + when( isDownRecPing & + downSubMsgHeadInfo(0).devIndex === 0.U & + downSubMsgHeadInfo(0).style === 0.U & + downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_INDEX + ){ + localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U + indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U) + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U + } .elsewhen( ~isDownRecPing & + downSubMsgHeadInfo(1).devIndex === 0.U & + downSubMsgHeadInfo(1).style === 0.U & + downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_INDEX + ){ //pong + localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U + indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U) + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } - //上行接收 获取右侧索引号 + // when( downRecParser.io.subMsgHeadReq.fire & + // downRecParser.io.subMsgHeadReq.bits.devIndex === 0.U & + // downRecParser.io.subMsgHeadReq.bits.style === 0.U & + // downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_INDEX ){ //设置顺序地址 + // localDevIndex := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U + // indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgHeadReq.bits.workCnt + 2.U) + // when( isDownRecPing ){ + // downSubMsgHeadInfo(0).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U + // } .otherwise{ //pong + // downSubMsgHeadInfo(1).workCnt := downRecParser.io.subMsgHeadReq.bits.workCnt + 1.U + // } + // } } @@ -382,34 +449,27 @@ trait SlaveParserIndex{ this: SlaveParserBase => trait SlaveParserRW{ this: SlaveParserBase => - // val isSeqIndexMatch = - // (downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex) - - // val downLgcAddress = Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) - // val isLgcIndexMatch = - // (downRecParser.io.subMsgReq.bits.isLgcIndex & - - - + val isDownLgcWorked = RegInit(false.B) + val isUpLgcWorked = RegInit(false.B) //下行接收 - when( downRecParser.io.subMsgReq.fire ){ + when( downRecParser.io.subMsgTailReq.fire ){ when( isDownRecPing ){ //override when( - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & isDownLgcWorked ) ) ) | + ( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) { //自身包//写操作或读写操作) - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } .otherwise{ //pong //override when( - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE ) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE) | (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE ) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & isDownLgcWorked ) ) ) | + ( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) { //自身包//写操作或读写操作 ) - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } } @@ -431,10 +491,10 @@ trait SlaveParserRW{ this: SlaveParserBase => val downTransLenCnt = RegInit(0.U) val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || ( downSubMsgInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || ( downSubMsgInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) @@ -463,14 +523,20 @@ trait SlaveParserRW{ this: SlaveParserBase => downTransLenCnt := downTransLenCnt - 1.U } + when( downRecParser.io.subMsgTailReq.fire ){ + isDownLgcWorked := false.B + } .elsewhen( isDownLgcAddrwAcquireTrans ){ + isDownLgcWorked := true.B + } + //组合逻辑 - when( downRecParser.io.subMsgReq.fire & ( - (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex + when( downRecParser.io.subMsgHeadReq.fire & ( + (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex )){//组合逻辑 - logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) + logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address ) } .elsewhen( downRecParser.io.data.fire & ( - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(0).isLgcIndex ) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgInfo(1).isLgcIndex ) + ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) )){//组合逻辑 logicAddrwNext := logicAddrw + 1.U } .otherwise{//组合逻辑 @@ -478,22 +544,22 @@ trait SlaveParserRW{ this: SlaveParserBase => } - when( downRecParser.io.subMsgReq.fire ){ //子包头装填 + when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填 when( - ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) ){ //常规寻址 - addrw := downRecParser.io.subMsgReq.bits.address - } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ //逻辑寻址 + addrw := downRecParser.io.subMsgHeadReq.bits.address + } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){ //逻辑寻址 addrw := acquireDownPhyAddrw } } .elsewhen( isWrite & downRecParser.io.data.fire ){ when( - ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) ){ addrw := addrw + 1.U - } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ + } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){ addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U ) } } @@ -521,27 +587,26 @@ trait SlaveParserRW{ this: SlaveParserBase => io.sram_w(3).dataw := downRecParser.io.data.bits - //上行接收 - when( upRecParser.io.subMsgReq.fire ){ + when( upRecParser.io.subMsgTailReq.fire ){ when( isUpRecPing ){ //override when( - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ){ //自身包//读或读写 - upSubMsgInfo(0).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } .otherwise{ //override when( - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD ) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) ) & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | - ( ( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD) | (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ){ //自身包//读或读写 ) - upSubMsgInfo(1).workCnt := upRecParser.io.subMsgReq.bits.workCnt + 1.U + upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } } @@ -578,24 +643,30 @@ trait SlaveParserRW{ this: SlaveParserBase => ) when( isUpLgcAddrrAcquireTrans & ( - (upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | + (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) )){ //装填计数器 upTransLenCnt := acquireUpTransLen } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){ upTransLenCnt := upTransLenCnt - 1.U } + when( upRecParser.io.subMsgTailReq.fire ){ + isUpLgcWorked := false.B + } .elsewhen( isUpLgcAddrrAcquireTrans ){ + isUpLgcWorked := true.B + } + //组合逻辑 - when( upRecParser.io.subMsgReq.fire & ( - (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex + when( upRecParser.io.subMsgHeadReq.fire & ( + (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex )){//组合逻辑 - logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) + logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address ) } .elsewhen( upRecParser.io.data.fire){ when( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).isLgcIndex ) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).isLgcIndex ) + (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) | + ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex ) ){//组合逻辑 logicAddrrNext := logicAddrr + 1.U } .otherwise{ @@ -612,20 +683,19 @@ trait SlaveParserRW{ this: SlaveParserBase => val isRDSM5 = addrr(14,11) === "b0110".U val isRDSM7 = addrr(14,11) === "b1000".U - val isSeqRead = ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) )) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) )) | - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) + (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) | + ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) | + (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | + ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ) ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire ) val isLgcRead = ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) + (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | + ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) ) ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire ) @@ -633,54 +703,26 @@ trait SlaveParserRW{ this: SlaveParserBase => - - - // when( upRecParser.io.subMsgReq.fire){ - // when( - // ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | - // ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) - // ){ - // addrr := upRecParser.io.subMsgReq.bits.address - // } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - // addrr := acquireUpPhyAddrr - // } - // } .elsewhen( isUpLgcAddrrAcquireTrans ){ - // when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - // addrr := acquireUpPhyAddrr - // } - // } - // .elsewhen( isLvdsEnR ){ - // assert(~isUpLgcAddrrAcquireTrans) - // when( - // ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | - // ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) - // ){ - // addrr := addrr + 1.U - // } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ - // addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) - // } - // } - when( - ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | - ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + ((upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgHeadReq.bits.isSeqIndex & upRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) ){ - when( upRecParser.io.subMsgReq.fire){ - addrr := upRecParser.io.subMsgReq.bits.address + when( upRecParser.io.subMsgHeadReq.fire){ + addrr := upRecParser.io.subMsgHeadReq.bits.address } .elsewhen(isLvdsEnR){ addrr := addrr + 1.U } } .elsewhen( isUpLgcAddrrAcquireTrans ){ when( - (upRecParser.io.subMsgReq.fire & (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex) | - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | + (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) ){ addrr := acquireUpPhyAddrr } } .elsewhen( isLvdsEnR & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(0).isLgcIndex )) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgInfo(1).isLgcIndex )) + (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) )){ assert(~isUpLgcAddrrAcquireTrans) addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) @@ -701,8 +743,8 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( - ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, - Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, + ( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) | (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, + Mux( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) ) upRecParser.io.data.ready := upRecFifo(0).io.enq.ready @@ -716,8 +758,8 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.bits := Mux( - ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, - Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, + ( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) | (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData, + Mux( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) ) @@ -765,18 +807,40 @@ trait SlaveParserRW{ this: SlaveParserBase => trait SlaveParserSync{ this: SlaveParserBase => + + // when( upRecParser.io.subMsgTailReq.fire ){ + // when( isUpRecPing ){ + // //override + // when( + // ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + // ( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + // ){ //自身包//读或读写 + // upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U + // } + // } .otherwise{ + // //override + // when( + // ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) | + // ( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + // ){ //自身包//读或读写 ) + // upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U + // } + // } + // } + + //下行接收 - when( downRecParser.io.subMsgReq.fire ){ + when( downRecParser.io.subMsgTailReq.fire ){ when( isDownRecPing ){ //override - when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包 - downSubMsgInfo(0).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + when( downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 + downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } .otherwise{ //pong //override - when( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_SYNC ) { //同步包 ) - downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U + when( downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 ) + downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } } @@ -817,8 +881,8 @@ trait SlaveParserSync{ this: SlaveParserBase => //下行接收 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & downSubMsgInfo(0).devIndex === 0.U & downSubMsgInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | - ( isDownRecPing & downSubMsgInfo(1).devIndex === 0.U & downSubMsgInfo(1).operator === SUBMSG_OPERATOR_SYNC ) + ( ~isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | + ( isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) ) val syncCnt = Reg(UInt(4.W)) diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index fceea55..b5e04c9 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -13,7 +13,8 @@ class SlaveRecParserIO extends Bundle{ val stateCurr = Output(UInt(4.W)) val frameReq = Valid( new FrameHeader ) - val subMsgReq = Valid( new SubMsgHeader ) + val subMsgHeadReq = Valid( new SubMsgHeader ) + val subMsgTailReq = Valid( new SubMsgTail ) val resp = Input(Bool()) val isError = Output(Bool()) @@ -30,9 +31,10 @@ class SlaveRecParser extends Module{ val STATE_HEADER = 1.U //长度/ /保留2bits //包类型 val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型 val STATE_PAYLOAD_DATA = 3.U //子报文数据 - val STATE_CRC = 4.U //CRC校验 - val STATE_ERROR = 5.U // - val STATE_WAIT = 6.U + val STATE_SUBMSG_TAIL = 4.U + val STATE_CRC = 5.U //CRC校验 + val STATE_ERROR = 6.U // + val STATE_WAIT = 7.U val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext @@ -44,7 +46,8 @@ class SlaveRecParser extends Module{ crc.io.isEnable := io.rec.fire & ( stateCurr === STATE_HEADER | stateCurr === STATE_SUBMSG_HEADER | - stateCurr === STATE_PAYLOAD_DATA + stateCurr === STATE_PAYLOAD_DATA | + stateCurr === STATE_SUBMSG_TAIL ) @@ -72,22 +75,25 @@ class SlaveRecParser extends Module{ val frameLenCnt = Reg(UInt(12.W)) //帧长度计数 - io.frameReq.valid := io.rec.fire & (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER) + io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC) val frameHeader = Reg(new FrameHeader) io.frameReq.bits.frameLenAim := frameHeader.frameLenAim io.frameReq.bits.frameStyle := frameHeader.frameStyle io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata - io.subMsgReq.valid := io.rec.fire & (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA) + io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA) + io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL) + val subMsgHeader = Reg(new SubMsgHeader) + val subMsgTail = Reg(new SubMsgTail) - io.subMsgReq.bits.devIndex := subMsgHeader.devIndex - io.subMsgReq.bits.style := subMsgHeader.style - io.subMsgReq.bits.address := subMsgHeader.address - io.subMsgReq.bits.operator := subMsgHeader.operator - io.subMsgReq.bits.length := subMsgHeader.length - io.subMsgReq.bits.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0) + io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex + io.subMsgHeadReq.bits.style := subMsgHeader.style + io.subMsgHeadReq.bits.address := subMsgHeader.address + io.subMsgHeadReq.bits.operator := subMsgHeader.operator + io.subMsgHeadReq.bits.length := subMsgHeader.length | io.rec.bits.tdata(7,0) + io.subMsgTailReq.bits.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0) when( io.rec.fire ){ when( stateCurr =/= stateNext ){ @@ -122,35 +128,43 @@ class SlaveRecParser extends Module{ when( io.rec.fire ){ - when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){ - frameHeader.frameLenAim := io.rec.bits.tdata << 4 - } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){ - frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4) - frameHeader.frameStyle := io.rec.bits.tdata(1,0) - } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){ - frameHeader.frameInfo := io.rec.bits.tdata << 8 - } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){ - frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata + when( stateCurr === STATE_HEADER ){ + when( lengthCnt === 0.U ){ + frameHeader.frameLenAim := io.rec.bits.tdata << 4 + } .elsewhen( lengthCnt === 1.U ){ + frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4) + frameHeader.frameStyle := io.rec.bits.tdata(1,0) + } .elsewhen( lengthCnt === 2.U ){ + frameHeader.frameInfo := io.rec.bits.tdata << 8 + } .elsewhen( lengthCnt === 3.U ){ + frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata + } + } + + when( stateCurr === STATE_SUBMSG_HEADER ){ + when(lengthCnt === 0.U ){ + subMsgHeader.devIndex := io.rec.bits.tdata << 6 + } .elsewhen( lengthCnt === 1.U ){ + subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2) + subMsgHeader.style := io.rec.bits.tdata(1,0) + } .elsewhen( lengthCnt === 2.U ){ + subMsgHeader.address := io.rec.bits.tdata << 8 + } .elsewhen( lengthCnt === 3.U ){ + subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata + } .elsewhen( lengthCnt === 4.U ){ + subMsgHeader.operator := io.rec.bits.tdata(7,4) + subMsgHeader.length := io.rec.bits.tdata(3,0) << 8 + } .elsewhen( lengthCnt === 5.U ){ + subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0) + } } - when( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 0.U ){ - subMsgHeader.devIndex := io.rec.bits.tdata << 6 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 1.U ){ - subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2) - subMsgHeader.style := io.rec.bits.tdata(1,0) - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 2.U ){ - subMsgHeader.address := io.rec.bits.tdata << 8 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 3.U ){ - subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 4.U ){ - subMsgHeader.operator := io.rec.bits.tdata(7,4) - subMsgHeader.length := io.rec.bits.tdata(3,0) << 8 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 5.U ){ - subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0) - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 6.U ){ - subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8 - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 7.U ){ - subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0) + when( stateCurr === STATE_SUBMSG_TAIL ){ + when(lengthCnt === 0.U ){ + subMsgTail.workCnt := io.rec.bits.tdata << 8 + } .elsewhen( lengthCnt === 1.U ){ + subMsgTail.workCnt := subMsgTail.workCnt | io.rec.bits.tdata(7,0) + } } } @@ -173,14 +187,19 @@ class SlaveRecParser extends Module{ )), STATE_HEADER ), ( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, - Mux( lengthCnt === (8-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER ) + Mux( lengthCnt === (6-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER ) ), STATE_SUBMSG_HEADER), - ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR, - Mux( lengthCnt === ( subMsgHeader.length - 1.U), - Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER - ), STATE_PAYLOAD_DATA ) + ( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR, + Mux( lengthCnt === ( subMsgHeader.length - 1.U), STATE_SUBMSG_TAIL, STATE_PAYLOAD_DATA ) ), STATE_PAYLOAD_DATA), + + ( stateCurr === STATE_SUBMSG_TAIL ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR, + Mux( lengthCnt === ( (2 - 1).U), + Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER + ),STATE_SUBMSG_TAIL ) + ), STATE_SUBMSG_TAIL), + ( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast, Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC ), diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 65fc363..5e6a4b6 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -15,7 +15,8 @@ class SlaveSendGenIO extends Bundle{ val frameReq = Flipped(Decoupled( new FrameHeader )) - val subMsgReq = Flipped(Decoupled( new SubMsgTxInfo )) + val subMsgHeadReq = Flipped(Decoupled( new SubMsgTxInfo )) + val subMsgTailReq = Flipped(Decoupled( new SubMsgTail )) val send = Decoupled(new AXIS_Bundle(8)) @@ -39,8 +40,8 @@ class SlaveSendGen extends Module{ val STATE_FRAME_HEADER = 1.U //长度/ /保留2bits //包类型 val STATE_SUBMSG_HEADER = 2.U val STATE_SUBMSG_DATA = 3.U - val STATE_CRC = 4.U //CRC校验 - //val STATE_ERROR = 5.U + val STATE_SUBMSG_TAIL = 4.U + val STATE_CRC = 5.U //CRC校验 val STATE_WAIT = 6.U @@ -64,22 +65,22 @@ class SlaveSendGen extends Module{ val frameInfo = Reg(new FrameHeader) - val subMsgInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } + val subMsgHeadInfo = Reg(new SubMsgTxInfo) + val subMsgTailInfo = Reg(new SubMsgTail) + - val isPingFill = RegInit(false.B) - val isPingEmit = RegInit(false.B) when( io.frameReq.fire ){ frameInfo := io.frameReq.bits } - when( io.subMsgReq.fire ){ - when( isPingFill ){ - subMsgInfo(0) := io.subMsgReq.bits - } .otherwise{ - subMsgInfo(1) := io.subMsgReq.bits - } + when( io.subMsgHeadReq.fire ){ + subMsgHeadInfo := io.subMsgHeadReq.bits + } + + when( io.subMsgTailReq.fire ){ + subMsgTailInfo := io.subMsgTailReq.bits } @@ -90,7 +91,7 @@ class SlaveSendGen extends Module{ when( io.send.fire ){ when( stateCurr === STATE_FRAME_HEADER ){ frameLenCnt := 0.U - } .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA ){ + } .elsewhen( stateCurr === STATE_SUBMSG_HEADER || stateCurr === STATE_SUBMSG_DATA || stateCurr === STATE_SUBMSG_TAIL ){ frameLenCnt := frameLenCnt + 1.U } } @@ -104,36 +105,38 @@ class SlaveSendGen extends Module{ - val subMsgInfoSel = Mux( isPingEmit, subMsgInfo(0), subMsgInfo(1) ) - - - io.frameReq.ready := true.B - io.subMsgReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER - + io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER + io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL stateNext := Mux1H(Seq( (stateCurr === STATE_IDLE) -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ), (stateCurr === STATE_FRAME_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux( frameInfo.frameStyle === FRAME_STYLE_COMMON, - Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), + Mux(io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), STATE_CRC ), STATE_FRAME_HEADER), STATE_FRAME_HEADER ), - (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), + (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (6-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER), + (stateCurr === STATE_SUBMSG_DATA) -> Mux( io.send.fire, - Mux( lengthCnt === subMsgInfoSel.length-1.U, //已经发送完成该子报文 + Mux( lengthCnt === subMsgHeadInfo.length-1.U, STATE_SUBMSG_TAIL, STATE_SUBMSG_DATA ), //已经发送完成该子报文 + STATE_SUBMSG_DATA ), + + (stateCurr === STATE_SUBMSG_TAIL) -> Mux( io.send.fire, + Mux( lengthCnt === (2-1).U, //已经发送完成该子报文尾 Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC - Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文 - STATE_SUBMSG_DATA - ), STATE_SUBMSG_DATA ), + Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文 + STATE_SUBMSG_TAIL + ), STATE_SUBMSG_TAIL ), + (stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC), // (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR), - (stateCurr === STATE_WAIT) -> Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), + (stateCurr === STATE_WAIT) -> Mux( io.subMsgHeadReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT), )) - io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 0.U) - io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 1.U) + io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 0.U) + io.data(1).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgHeadInfo.source === 1.U) assert( ~(io.data(0).ready & ~io.data(0).valid) ) assert( ~(io.data(1).ready & ~io.data(1).valid) ) @@ -143,7 +146,8 @@ class SlaveSendGen extends Module{ io.send.valid := (stateCurr === STATE_FRAME_HEADER) | (stateCurr === STATE_SUBMSG_HEADER) | - (stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgInfoSel.source === 0.U) | (io.data(1).valid & subMsgInfoSel.source === 1.U) )) | + (stateCurr === STATE_SUBMSG_DATA & ( (io.data(0).valid & subMsgHeadInfo.source === 0.U) | (io.data(1).valid & subMsgHeadInfo.source === 1.U) )) | + (stateCurr === STATE_SUBMSG_TAIL) | (stateCurr === STATE_CRC) @@ -155,25 +159,29 @@ class SlaveSendGen extends Module{ )) val tdata_submsg_header = Mux1H(Seq( - (lengthCnt === 0.U) -> subMsgInfoSel.devIndex(13,6), - (lengthCnt === 1.U) -> Cat( subMsgInfoSel.devIndex(5,0), subMsgInfoSel.style), - (lengthCnt === 2.U) -> subMsgInfoSel.address(15,8), - (lengthCnt === 3.U) -> subMsgInfoSel.address(7,0), - (lengthCnt === 4.U) -> Cat(subMsgInfoSel.operator, subMsgInfoSel.length(11,8)), - (lengthCnt === 5.U) -> subMsgInfoSel.length(7,0), - (lengthCnt === 6.U) -> subMsgInfoSel.workCnt(15,8), - (lengthCnt === 7.U) -> subMsgInfoSel.workCnt(7,0), + (lengthCnt === 0.U) -> subMsgHeadInfo.devIndex(13,6), + (lengthCnt === 1.U) -> Cat( subMsgHeadInfo.devIndex(5,0), subMsgHeadInfo.style), + (lengthCnt === 2.U) -> subMsgHeadInfo.address(15,8), + (lengthCnt === 3.U) -> subMsgHeadInfo.address(7,0), + (lengthCnt === 4.U) -> Cat(subMsgHeadInfo.operator, subMsgHeadInfo.length(11,8)), + (lengthCnt === 5.U) -> subMsgHeadInfo.length(7,0), )) val tdata_submsg_data = Mux1H(Seq( - (subMsgInfoSel.source === 0.U) -> io.data(0).bits, - (subMsgInfoSel.source === 1.U) -> io.data(1).bits, + (subMsgHeadInfo.source === 0.U) -> io.data(0).bits, + (subMsgHeadInfo.source === 1.U) -> io.data(1).bits, + )) + + val tdata_submsg_tail = Mux1H(Seq( + (lengthCnt === 0.U) -> subMsgTailInfo.workCnt(15,8), + (lengthCnt === 1.U) -> subMsgTailInfo.workCnt( 7,0), )) crc.io.dataIn := Mux1H(Seq( (stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header, (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header, (stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data, + (stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail, )) @@ -188,6 +196,7 @@ class SlaveSendGen extends Module{ (stateCurr === STATE_FRAME_HEADER) -> tdata_frame_header, (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header, (stateCurr === STATE_SUBMSG_DATA) -> tdata_submsg_data, + (stateCurr === STATE_SUBMSG_TAIL) -> tdata_submsg_tail, (stateCurr === STATE_CRC) -> tdata_crc, )) From 8a0533738cbaacac25c725685a996cffae3b53bc Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 25 Jun 2025 10:48:37 +0800 Subject: [PATCH 18/41] =?UTF-8?q?workcnt=E6=9C=89=E4=B8=80=E4=BA=9B?= =?UTF-8?q?=E9=94=99=E8=AF=AF=EF=BC=8C=E5=A4=87=E4=BB=BD=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 20 +++++++++++++++----- tb/shinTest/gen_pkt.py | 16 ++++++++-------- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 7cff8eb..984677f 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -9,7 +9,7 @@ //`define ENABLE_EXCHG_DATA_SEQ0_TEST //`define ENABLE_EXCHG_DATA_SEQ1_TEST -//`define ENABLE_EXCHG_DATA_SEQ2_TEST +`define ENABLE_EXCHG_DATA_SEQ2_TEST //`define ENABLE_EXCHG_DATA_SEQ3_TEST //`define ENABLE_BC_R_TEST @@ -17,7 +17,7 @@ //`define ENABLE_BC_RW_TEST `define ENABLE_SYNC_TEST -`define ENABLE_SYNC_SIG0_TEST +//`define ENABLE_SYNC_SIG0_TEST //`define ENABLE_SYNC_SIG1_TEST //`define ENABLE_RESET_TEST @@ -427,7 +427,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in $realtime, ((sidx >= 5)? ((sidx >= 10)? (sidx - 10):(sidx - 5)):sidx), txBuf[0], txBuf[1], ((txBuf[2] == 0)? "Write":" Read"), slength); - if ( ((saddress == 16'h0800) + if ( ((saddress == 16'h0800) || (saddress == 16'h1000) || (saddress == 16'h1800) || (saddress == 16'h2000) @@ -448,7 +448,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in $fwrite(spidata_file, "\n"); _pos = 4 + _pos; for (; _pos < slength; ) begin - for (integer _k = 0; _k < 8; _k++) begin + for (integer _k = 0; _k < 6; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); _len = txBuf[_pos + 5] + (txBuf[_pos + 4] & 8'h0f) * 256; @@ -459,7 +459,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in end $fwrite(spidata_file, "\n{{ "); - _pos = _pos + 8; + _pos = _pos + 6; for (integer _k = 0; _k < _len; _k++) begin if (scmd == 0) begin $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); @@ -474,6 +474,16 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in end $fwrite(spidata_file, "}}\n"); _pos = _pos + _len; + + for (integer _k = 0; _k < 2; _k++) begin + if (scmd == 0) begin + $fwrite(spidata_file, "%02h ", txBuf[_k + _pos]); + end else begin + $fwrite(spidata_file, "%02h ", rxBuf[_k + _pos]); + end + end + _pos = _pos + 2; + $fwrite(spidata_file, "\n"); end end else begin for (integer i=0; i Date: Wed, 25 Jun 2025 15:25:53 +0800 Subject: [PATCH 19/41] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E4=B8=8A=E8=A1=8C?= =?UTF-8?q?=E5=AD=90=E6=8A=A5=E6=96=87=E5=B0=BE=E4=BC=A0=E9=80=92=E9=97=AE?= =?UTF-8?q?=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 25 ++++++++++++++++--- .../scala/backBoard/shin/SlaveSendGen.scala | 1 + tb/shinTest/ShinTopSpiTb.v | 2 +- 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index d611480..49daa22 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -379,9 +379,28 @@ abstract class SlaveParserBase extends Module{ } } - when( upSendGen.io.subMsgHeadReq.fire ){ //ready + when( upSendGen.io.subMsgTailReq.fire ){ + when( isUpSendPing ){ + assert( isUpSubMsgTailValid(0) ) + isUpSubMsgTailValid(0) := false.B + } .otherwise{ + assert( isUpSubMsgTailValid(1) ) + isUpSubMsgTailValid(1) := false.B + } + } .elsewhen( upRecParser.io.subMsgTailReq.fire ){ + when( isUpRecPing ){ + assert( ~isUpSubMsgTailValid(0) ) + isUpSubMsgTailValid(0) := true.B + } .otherwise{ + assert( ~isUpSubMsgTailValid(1) ) + isUpSubMsgTailValid(1) := true.B + } + } + + + when( upSendGen.io.subMsgTailReq.fire ){ //ready isUpSendPing := ~isUpSendPing - }.elsewhen( upRecParser.io.subMsgHeadReq.fire ){ + }.elsewhen( upRecParser.io.subMsgTailReq.fire ){ isUpRecPing := ~isUpRecPing } @@ -739,7 +758,7 @@ trait SlaveParserRW{ this: SlaveParserBase => )) - when( ~isUpRecPing ){ //req fire 后 已经反相 + when( isUpRecPing ){ upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 5e6a4b6..8e43196 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -108,6 +108,7 @@ class SlaveSendGen extends Module{ io.frameReq.ready := true.B io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL & stateNext === STATE_SUBMSG_TAIL + assert( ~(io.subMsgTailReq.ready & ~io.subMsgTailReq.valid) ) stateNext := Mux1H(Seq( diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 984677f..d298a25 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -238,7 +238,7 @@ ShinTop s_ShinTop_slv3( initial begin clock = 0; clk8x = 0; - reset = 0; + reset = 1; _reset_deactive = 1'b0; From 063e446ff9b738c78df945e284490482089b1aa6 Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 25 Jun 2025 15:48:39 +0800 Subject: [PATCH 20/41] =?UTF-8?q?=E6=B5=8B=E8=AF=95=E5=90=8E=E5=8F=91?= =?UTF-8?q?=E7=8E=B0workcnt=E5=B7=A5=E4=BD=9C=E4=BA=86,=E4=BD=86=E6=98=AF?= =?UTF-8?q?=E4=BA=A4=E6=8D=A2=E6=95=B0=E6=8D=AE=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index d298a25..2061c60 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -24,7 +24,7 @@ //`define ENABLE_EBMMU_TC1_TEST //`define ENABLE_EBMMU_TC2_TEST //`define ENABLE_EBMMU_TC3_TEST -`define ENABLE_EBMMU_TC4_TEST +//`define ENABLE_EBMMU_TC4_TEST module ShinTopSpiTb( From a19dd8ee279711c34bc17678fa8f302faecb2848 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 25 Jun 2025 16:24:21 +0800 Subject: [PATCH 21/41] =?UTF-8?q?pingpong=E6=8C=87=E9=92=88=E4=BF=AE?= =?UTF-8?q?=E5=A4=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 49daa22..03aeb67 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -510,10 +510,10 @@ trait SlaveParserRW{ this: SlaveParserBase => val downTransLenCnt = RegInit(0.U) val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | - ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | - ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | - ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) @@ -554,8 +554,8 @@ trait SlaveParserRW{ this: SlaveParserBase => )){//组合逻辑 logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address ) } .elsewhen( downRecParser.io.data.fire & ( - ( ~isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | - ( isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) )){//组合逻辑 logicAddrwNext := logicAddrw + 1.U } .otherwise{//组合逻辑 @@ -663,8 +663,8 @@ trait SlaveParserRW{ this: SlaveParserBase => when( isUpLgcAddrrAcquireTrans & ( (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | - (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | - ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) )){ //装填计数器 upTransLenCnt := acquireUpTransLen } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){ @@ -684,8 +684,8 @@ trait SlaveParserRW{ this: SlaveParserBase => logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address ) } .elsewhen( upRecParser.io.data.fire){ when( - (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) | - ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex ) + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex ) ){//组合逻辑 logicAddrrNext := logicAddrr + 1.U } .otherwise{ @@ -704,17 +704,17 @@ trait SlaveParserRW{ this: SlaveParserBase => val isSeqRead = ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) | - ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) | - (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | - ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) | + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ) ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire ) val isLgcRead = ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | - ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) ) ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire ) @@ -734,14 +734,14 @@ trait SlaveParserRW{ this: SlaveParserBase => } .elsewhen( isUpLgcAddrrAcquireTrans ){ when( (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | - (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | - ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) ){ addrr := acquireUpPhyAddrr } } .elsewhen( isLvdsEnR & ( - (~isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | - ( isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) )){ assert(~isUpLgcAddrrAcquireTrans) addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U ) @@ -900,8 +900,8 @@ trait SlaveParserSync{ this: SlaveParserBase => //下行接收 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | - ( isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) + ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | + ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) ) val syncCnt = Reg(UInt(4.W)) From 7c323711441730973b6aad368d1765108b8b7860 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 09:34:43 +0800 Subject: [PATCH 22/41] =?UTF-8?q?=E6=B5=8B=E8=AF=95=E5=8F=91=E7=8E=B0?= =?UTF-8?q?=E5=90=8C=E6=AD=A5=E7=9A=84=E5=91=BD=E4=BB=A4=E4=B8=8D=E8=83=BD?= =?UTF-8?q?=E6=AD=A3=E5=B8=B8=E5=B7=A5=E4=BD=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 2061c60..0a2f524 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -7,9 +7,9 @@ //`define ENABLE_SM1_SEND_TEST //`define ENABLE_SMx_SEND_TEST -//`define ENABLE_EXCHG_DATA_SEQ0_TEST +`define ENABLE_EXCHG_DATA_SEQ0_TEST //`define ENABLE_EXCHG_DATA_SEQ1_TEST -`define ENABLE_EXCHG_DATA_SEQ2_TEST +//`define ENABLE_EXCHG_DATA_SEQ2_TEST //`define ENABLE_EXCHG_DATA_SEQ3_TEST //`define ENABLE_BC_R_TEST @@ -17,8 +17,8 @@ //`define ENABLE_BC_RW_TEST `define ENABLE_SYNC_TEST -//`define ENABLE_SYNC_SIG0_TEST -//`define ENABLE_SYNC_SIG1_TEST +`define ENABLE_SYNC_SIG0_TEST +`define ENABLE_SYNC_SIG1_TEST //`define ENABLE_RESET_TEST //`define ENABLE_EBMMU_TC1_TEST @@ -956,7 +956,7 @@ initial begin `include "seq_1_pkt.vh" - spi_trans( (16'h1800), (`SPI_READ), (64), (`IF_IDX(1$fdisplay(spidata_file, "嗅探：使用SM0"); + spi_trans( (16'h1800), (`SPI_READ), (64), (`IF_IDX(1)) ); $fdisplay(spidata_file, "-嗅探前，检查链路状态寄存器"); //spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(0)) ); spi_trans( (16'h00c0), (`SPI_READ), (4), (`IF_IDX(1)) ); @@ -970,11 +970,11 @@ initial begin `include "detect_pkt.vh" $fdisplay(spidata_file, "-嗅探后，检查链路状态寄存器"); - //spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(0)) ); + //spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(0)) ); spi_trans( (16'h00c0), (`SPI_READ), (4), (`IF_IDX(1)) ); spi_trans( (16'h00c0), (`SPI_READ), (4), (`IF_IDX(2)) ); spi_trans( (16'h00c0), (`SPI_READ), (4), (`IF_IDX(3)) ); - spi_trans( (16'h00c0), (`SPI_READ), (4), (`IF_IDX(4)) );)) ); + spi_trans( (16'h00c0), (`SPI_READ), (4), (`IF_IDX(4)) ); spi_trans( (16'h0800), (`SPI_READ), (64), (`IF_IDX(2)) ); spi_trans( (16'h2800), (`SPI_READ), (64), (`IF_IDX(3)) ); spi_trans( (16'h3800), (`SPI_READ), (64), (`IF_IDX(4)) ); From 88c2b6b1e0266af6a077c0222667aee55a764bd2 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 10:53:55 +0800 Subject: [PATCH 23/41] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E5=90=8C=E6=AD=A5?= =?UTF-8?q?=E5=8C=85=E7=9A=84=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 79b18e1..a02e09c 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -478,7 +478,7 @@ if __name__ == '__main__': genPkt.addSubPkt(0x0, 0, random.randint(0, 65535), 0xc, 12, b'\0'*12) - genPkt.addBeforeExc(genEnableInsertTimeCode(0xc)) + genPkt.addBeforeExc(genEnableInsertTimeCode(0xa)) gen_file_def = "sync_pkt" sm_idx = 0 From 672cc519bb738e330d3a4914bd7bc8d8831ff8c9 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 11:12:18 +0800 Subject: [PATCH 24/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=AF=B9RESET=E4=BF=A1?= =?UTF-8?q?=E5=8F=B7=E7=9A=84=E6=B5=8B=E8=AF=95,=E7=9B=AE=E5=89=8D?= =?UTF-8?q?=E8=BF=98=E6=98=AF=E4=BD=BF=E7=94=A8=E8=80=81=E7=89=88=E6=9C=AC?= =?UTF-8?q?=E7=9A=84=E6=B5=8B=E8=AF=95=E6=96=B9=E5=BC=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 0a2f524..99275b3 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -19,7 +19,7 @@ `define ENABLE_SYNC_TEST `define ENABLE_SYNC_SIG0_TEST `define ENABLE_SYNC_SIG1_TEST -//`define ENABLE_RESET_TEST +`define ENABLE_RESET_TEST //`define ENABLE_EBMMU_TC1_TEST //`define ENABLE_EBMMU_TC2_TEST @@ -1192,8 +1192,11 @@ initial begin //复位系统 $fdisplay(spidata_file, "-复位系统"); txBuf[0+3] = 8'h01; - spi_trans( (16'h40), (`SPI_WRITE), (1), (`IF_IDX(0)) );//复位主站 - spi_trans( (16'h40), (`SPI_WRITE), (1), (`IF_IDX(2)) );//复位从站2 + txBuf[0+4] = 8'h00; + txBuf[0+5] = 8'h66; + txBuf[0+6] = 8'h79; + spi_trans( (16'h40), (`SPI_WRITE), (4), (`IF_IDX(0)) );//复位主站 + spi_trans( (16'h40), (`SPI_WRITE), (4), (`IF_IDX(2)) );//复位从站2 $fdisplay(spidata_file, "-配置系统"); From 18170d00dae5ab20ba5f180fd9cbea1fb0648032 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 16:37:12 +0800 Subject: [PATCH 25/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E7=94=9F=E6=88=90?= =?UTF-8?q?=E4=BB=8E=E7=AB=99=E9=80=A0SM=E6=95=B0=E6=8D=AE=E7=9A=84python?= =?UTF-8?q?=E4=BB=A3=E7=A0=81,=E7=94=9F=E6=88=90verilog=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E4=BB=A3=E7=A0=81;=E4=BF=AE=E6=94=B9=E7=9B=B8=E5=85=B3?= =?UTF-8?q?=E7=9A=84=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B;=E4=BF=AE?= =?UTF-8?q?=E6=94=B9=E6=89=93=E5=8D=B0=E7=9A=84=E8=BE=93=E5=87=BA=E4=BF=A1?= =?UTF-8?q?=E6=81=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 74 +++++++++++++++++--------------------- tb/shinTest/gen_pkt.py | 54 +++++++++++++++++++++++++--- 2 files changed, 83 insertions(+), 45 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 99275b3..8304563 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -9,7 +9,7 @@ `define ENABLE_EXCHG_DATA_SEQ0_TEST //`define ENABLE_EXCHG_DATA_SEQ1_TEST -//`define ENABLE_EXCHG_DATA_SEQ2_TEST +`define ENABLE_EXCHG_DATA_SEQ2_TEST //`define ENABLE_EXCHG_DATA_SEQ3_TEST //`define ENABLE_BC_R_TEST @@ -17,9 +17,9 @@ //`define ENABLE_BC_RW_TEST `define ENABLE_SYNC_TEST -`define ENABLE_SYNC_SIG0_TEST -`define ENABLE_SYNC_SIG1_TEST -`define ENABLE_RESET_TEST +//`define ENABLE_SYNC_SIG0_TEST +//`define ENABLE_SYNC_SIG1_TEST +//`define ENABLE_RESET_TEST //`define ENABLE_EBMMU_TC1_TEST //`define ENABLE_EBMMU_TC2_TEST @@ -457,6 +457,35 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in _len = rxBuf[_pos + 5] + (rxBuf[_pos + 4] & 8'h0f) * 256; end end + + begin:PRINT_PKT_COMMENT + integer dev; + integer addr_type; + integer addr; + integer cmd; + integer len; + + if (scmd == 0) begin + addr_type = txBuf[_pos + 1] & 8'h3; + dev = txBuf[_pos] * 256 + ((txBuf[_pos + 1] >> 2) & 8'hff); + addr = txBuf[_pos + 2] * 256 + (txBuf[_pos + 3] & 8'hff); + cmd = (txBuf[_pos + 4] >> 4) & 8'h0f; + len = (txBuf[_pos + 4] & 8'h0f) * 256 + (txBuf[_pos + 5] & 8'hff); + end else begin + addr_type = rxBuf[_pos + 1] & 8'h3; + dev = rxBuf[_pos] * 256 + ((rxBuf[_pos + 1] >> 2) & 8'hff); + addr = rxBuf[_pos + 2] * 256 + (rxBuf[_pos + 3] & 8'hff); + cmd = (rxBuf[_pos + 4] >> 4) & 8'h0f; + len = (rxBuf[_pos + 4] & 8'h0f) * 256 + (rxBuf[_pos + 5] & 8'hff); + end + + if (addr_type == 0) + $fwrite(spidata_file, "// type:%3d dev:%3d addr:0x%04x cmd:0x%1x len:%3d", addr_type, dev, addr[15:0], cmd[3:0], len); + else begin + addr = dev * 65536 + addr; + $fwrite(spidata_file, "// type:%3d addr:0x08x cmd:0x%1x len:%3d", addr_type, addr, cmd[3:0], len); + end + end $fwrite(spidata_file, "\n{{ "); _pos = _pos + 6; @@ -991,43 +1020,6 @@ initial begin $fdisplay(spidata_file, "\n\n测试用例：交换数据读dev1_sm1/dev2_sm3/dev3_sm5/dev4_sm7"); $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); - txBuf[3] = 8'h80; - txBuf[4] = 8'h00; - spi_trans((16'h0306), (`SPI_WRITE), (2), (`IF_IDX(1)) );//dev1_sm1 - - txBuf[3] = 8'h98; - txBuf[4] = 8'h00; - spi_trans((16'h030e), (`SPI_WRITE), (2), (`IF_IDX(2)) );//dev2_sm3 - - txBuf[3] = 8'h81; - txBuf[4] = 8'h00; - spi_trans((16'h0316), (`SPI_WRITE), (2), (`IF_IDX(3)) );//dev2_sm3 - - txBuf[3] = 8'h8c; - txBuf[4] = 8'h00; - spi_trans((16'h031e), (`SPI_WRITE), (2), (`IF_IDX(4)) );//dev2_sm3 - - - for (integer i=0; i < 128; i++) begin - txBuf[i + 3] = i + 1; - end - spi_trans( (16'h1000), (`SPI_WRITE), (128), (`IF_IDX(1)) ); - - for (integer i=0; i < 152; i++) begin - txBuf[i + 3] = i + 2; - end - spi_trans( (16'h2000), (`SPI_WRITE), (152), (`IF_IDX(2)) ); - - for (integer i=0; i < 129; i++) begin - txBuf[i + 3] = i + 3; - end - spi_trans( (16'h3000), (`SPI_WRITE), (129), (`IF_IDX(3)) ); - - for (integer i=0; i < 140; i++) begin - txBuf[i + 3] = i + 4; - end - spi_trans( (16'h4000), (`SPI_WRITE), (140), (`IF_IDX(4)) ); - `include "seq_2_pkt.vh" _t_end = $realtime; diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index a02e09c..caaff8a 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -231,7 +231,48 @@ def genCheckInsertTimeCode(): return '''\n//检查替换时间戳替换地址\n'''\ + '''$fdisplay(spidata_file, "--检查时间戳插入");\n'''\ + '''spi_trans( (16'h24), (`SPI_READ), (2), (`IF_IDX(0)) ); //检查替换时间戳替换地址寄存器\n''' + +def genSlvSMWriteData(dev, sm, data_len, data = None): + smaddr = list() + for i in range(8): + smaddr.append(0x300 + i * 4 + 2) + if not ((sm == 1) or (sm == 3) or (sm == 5) or (sm == 7)): + #写入数据，lvds读；这个空间是lvds写，mcu读 + return '' + if data_len > 2032: + return '' + + if (data != None) and (len(data) != 0) and (len(data) < data_len): + return '' + if (data == None) or (len(data) == 0): + data = list() + for i in range(data_len): + data.append((i + dev) & 0xff) + + code = '''txBuf[3] = 8'h%02x;\n'''%(data_len & 0xff, )\ + + '''txBuf[4] = 8'h%02x;\n'''%(int(data_len/256) & 0xff,)\ + + '''spi_trans((16'h0%04x), (`SPI_WRITE), (2), (`IF_IDX(%d)) );\n'''%(smaddr[sm], dev) + + for i in range(data_len): + code = code + '''txBuf[%d + 3] = 8'h%02x;\n'''%(i, data[i]) + + code = code + '''spi_trans( (16'h%04x), (`SPI_WRITE), (%d), (`IF_IDX(%d)) );\n'''%(0x800 + sm * 2048, data_len, dev) + return code + +def genSlvSMReadData(dev, sm, data_len): + if not ((sm == 0) or (sm == 2) or (sm == 4) or (sm == 6)): + #写入数据，lvds读；这个空间是lvds写，mcu读 + return '' + if data_len > 2032: + return '' + + code = "" + code = code + '''spi_trans( (16'h%04x), (`SPI_READ), (%d), (`IF_IDX(%d)) );\n'''%(0x800 + sm * 2048, data_len, dev) + + return code + + if __name__ == '__main__': genPkt = GenPkt() @@ -418,12 +459,17 @@ if __name__ == '__main__': #>>>>>>普通数据包2 genPkt.clean() genPkt.setPktType(0) - + + genPkt.addBeforeExc( genSlvSMWriteData(3, 1, 129) + + genSlvSMWriteData(4, 1, 140) + + genSlvSMWriteData(1, 1, 128) + + genSlvSMWriteData(2, 1, 152)) + #subPkt参数：索引、索引类型、地址、命令、长度、数据 - genPkt.addSubPkt(3, 0, 0x3000, 0x0, 129, b"\0"*129) - genPkt.addSubPkt(4, 0, 0x4000, 0x0, 140, b"\0"*140) + genPkt.addSubPkt(3, 0, 0x1000, 0x0, 129, b"\0"*129) + genPkt.addSubPkt(4, 0, 0x1000, 0x0, 140, b"\0"*140) genPkt.addSubPkt(1, 0, 0x1000, 0x0, 128, b"\0"*128) - genPkt.addSubPkt(2, 0, 0x2000, 0x0, 152, b"\0"*152) + genPkt.addSubPkt(2, 0, 0x1000, 0x0, 152, b"\0"*152) genPkt.addSubPkt(1, 0, 0x0306, 0x0, 2, b"\0"*2) genPkt.addSubPkt(2, 0, 0x030e, 0x0, 2, b"\0"*2) genPkt.addSubPkt(3, 0, 0x0316, 0x0, 2, b"\0"*2) From aa73bb3d99d5ee65bf9a9192ec82c941a26b0647 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 17:24:35 +0800 Subject: [PATCH 26/41] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E4=BB=A3=E7=A0=81?= =?UTF-8?q?=E9=94=99=E8=AF=AF,=E5=A2=9E=E5=8A=A0ebmmu=20=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 58 +++++++++++++------------------------- tb/shinTest/gen_pkt.py | 26 +++++++++++++++++ 2 files changed, 46 insertions(+), 38 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 8304563..580c433 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -7,9 +7,9 @@ //`define ENABLE_SM1_SEND_TEST //`define ENABLE_SMx_SEND_TEST -`define ENABLE_EXCHG_DATA_SEQ0_TEST +//`define ENABLE_EXCHG_DATA_SEQ0_TEST //`define ENABLE_EXCHG_DATA_SEQ1_TEST -`define ENABLE_EXCHG_DATA_SEQ2_TEST +//`define ENABLE_EXCHG_DATA_SEQ2_TEST //`define ENABLE_EXCHG_DATA_SEQ3_TEST //`define ENABLE_BC_R_TEST @@ -25,6 +25,7 @@ //`define ENABLE_EBMMU_TC2_TEST //`define ENABLE_EBMMU_TC3_TEST //`define ENABLE_EBMMU_TC4_TEST +`define ENABLE_EBMMU_TC5_TEST module ShinTopSpiTb( @@ -467,13 +468,13 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in if (scmd == 0) begin addr_type = txBuf[_pos + 1] & 8'h3; - dev = txBuf[_pos] * 256 + ((txBuf[_pos + 1] >> 2) & 8'hff); + dev = (txBuf[_pos] >> 2) * 256 + ((txBuf[_pos + 1] >> 2) & 8'hff); addr = txBuf[_pos + 2] * 256 + (txBuf[_pos + 3] & 8'hff); cmd = (txBuf[_pos + 4] >> 4) & 8'h0f; len = (txBuf[_pos + 4] & 8'h0f) * 256 + (txBuf[_pos + 5] & 8'hff); end else begin addr_type = rxBuf[_pos + 1] & 8'h3; - dev = rxBuf[_pos] * 256 + ((rxBuf[_pos + 1] >> 2) & 8'hff); + dev = (rxBuf[_pos] >> 2) * 256 + ((rxBuf[_pos + 1] >> 2) & 8'hff); addr = rxBuf[_pos + 2] * 256 + (rxBuf[_pos + 3] & 8'hff); cmd = (rxBuf[_pos + 4] >> 4) & 8'h0f; len = (rxBuf[_pos + 4] & 8'h0f) * 256 + (rxBuf[_pos + 5] & 8'hff); @@ -483,7 +484,7 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in $fwrite(spidata_file, "// type:%3d dev:%3d addr:0x%04x cmd:0x%1x len:%3d", addr_type, dev, addr[15:0], cmd[3:0], len); else begin addr = dev * 65536 + addr; - $fwrite(spidata_file, "// type:%3d addr:0x08x cmd:0x%1x len:%3d", addr_type, addr, cmd[3:0], len); + $fwrite(spidata_file, "// type:%3d addr:0x%08x cmd:0x%1x len:%3d", addr_type, addr, cmd[3:0], len); end end @@ -1368,47 +1369,28 @@ initial begin $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用4"); $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); - txBuf[3] = 8'h80; - txBuf[4] = 8'h00; - spi_trans((16'h0306), (`SPI_WRITE), (2), (`IF_IDX(1)) );//dev1_sm1 + `include "ebmmu_tc4_settings.vh" - txBuf[3] = 8'h98; - txBuf[4] = 8'h00; - spi_trans((16'h030e), (`SPI_WRITE), (2), (`IF_IDX(2)) );//dev2_sm3 + `include "ebmmu_tc4_read.vh" - txBuf[3] = 8'h81; - txBuf[4] = 8'h00; - spi_trans((16'h0316), (`SPI_WRITE), (2), (`IF_IDX(3)) );//dev2_sm3 + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end +`endif - txBuf[3] = 8'h8c; - txBuf[4] = 8'h00; - spi_trans((16'h031e), (`SPI_WRITE), (2), (`IF_IDX(4)) );//dev2_sm3 - - - for (integer i=0; i < 128; i++) begin - txBuf[i + 3] = i + 1; - end - spi_trans( (16'h1000), (`SPI_WRITE), (128), (`IF_IDX(1)) ); - - for (integer i=0; i < 152; i++) begin - txBuf[i + 3] = i + 2; - end - spi_trans( (16'h2000), (`SPI_WRITE), (152), (`IF_IDX(2)) ); - - for (integer i=0; i < 129; i++) begin - txBuf[i + 3] = i + 3; - end - spi_trans( (16'h3000), (`SPI_WRITE), (129), (`IF_IDX(3)) ); - - for (integer i=0; i < 140; i++) begin - txBuf[i + 3] = i + 4; - end - spi_trans( (16'h4000), (`SPI_WRITE), (140), (`IF_IDX(4)) ); +`ifdef ENABLE_EBMMU_TC5_TEST + begin:EBMMU_TC5_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用4"); + $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); `include "ebmmu_tc4_settings.vh" `include "ebmmu_tc4_read.vh" + `include "ebmmu_tc5_read.vh" + _t_end = $realtime; $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); end diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index caaff8a..6809c54 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1267,6 +1267,11 @@ if __name__ == '__main__': genPkt.clean() genPkt.setPktType(0) + genPkt.addBeforeExc( genSlvSMWriteData(1, 1, 0x80) + + genSlvSMWriteData(2, 3, 0x98) + + genSlvSMWriteData(3, 5, 0x81) + + genSlvSMWriteData(4, 7, 0x8c)) + #subPkt参数：索引、索引类型、地址、命令、长度、数据 data = [0,] * 30 @@ -1372,3 +1377,24 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 550 + + genPkt.addSubPkt(0x1000, 2, 0x0058, 0x0, 0x80+0x98+0x81+0x8c, data) + + gen_file_def = "ebmmu_tc5_read" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + From ee5502a9aa8468424b8af7a3170777a0e0f833a1 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 19:02:38 +0800 Subject: [PATCH 27/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0ebmmu=20test=206,?= =?UTF-8?q?=E5=86=99=E5=85=A5=E7=9A=84=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 21 ++++++- tb/shinTest/gen_pkt.py | 124 +++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+), 2 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 580c433..0b31fb5 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -25,7 +25,8 @@ //`define ENABLE_EBMMU_TC2_TEST //`define ENABLE_EBMMU_TC3_TEST //`define ENABLE_EBMMU_TC4_TEST -`define ENABLE_EBMMU_TC5_TEST +//`define ENABLE_EBMMU_TC5_TEST +`define ENABLE_EBMMU_TC6_TEST module ShinTopSpiTb( @@ -1382,7 +1383,7 @@ initial begin begin:EBMMU_TC5_TEST _t_start = $realtime; #1000 - $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用4"); + $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用5"); $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); `include "ebmmu_tc4_settings.vh" @@ -1396,6 +1397,22 @@ initial begin end `endif +`ifdef ENABLE_EBMMU_TC6_TEST + begin:EBMMU_TC6_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用6"); + $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); + + `include "ebmmu_tc6_settings.vh" + + `include "ebmmu_tc6_write.vh" + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end +`endif + #1000000 $display("Testcase Finished! Time Out !!!"); $fclose(spidata_file); diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 6809c54..83847d6 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1398,3 +1398,127 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + #-------------------------------------------------------------------------- + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU,测试用例6 + genPkt.clean() + genPkt.setPktType(0) + + addr_off = 0x58 + 0x80 + 0x98 + 0x81 + 0x8c + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + addr = addr_off + 0x0 + #print(hex(addr)) + data[0] = (addr & 0xff) + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x02 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x0228, 0x1, 10, data) + + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x0228, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc6_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 0x80 * 4 + for i in range(0x80 * 4): + data[i] = i & 0xff + + genPkt.addSubPkt(0x1000, 2, addr_off, 0x1, 0x80 * 4, data) + + gen_file_def = "ebmmu_tc6_write" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + +genSlvSMReadData(1, 0, 0x80) + +genSlvSMReadData(2, 0, 0x80) + +genSlvSMReadData(3, 0, 0x80) + +genSlvSMReadData(4, 0, 0x80)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + From fb233555682fc8bd41bf4d3ea3084e4fa0b0b717 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 20:33:32 +0800 Subject: [PATCH 28/41] =?UTF-8?q?=E5=B0=86=E7=AC=AC=E4=BA=8C=E4=B8=AAebmmu?= =?UTF-8?q?=E4=BF=AE=E6=94=B9=E4=B8=BA=E8=AF=BB=E5=86=99=E5=B1=9E=E6=80=A7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 83847d6..975f7af 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1441,7 +1441,7 @@ if __name__ == '__main__': data[6] = 0x80 data[7] = 0x00 - data[8] = 0x02 + data[8] = 0x03 data[9] = 0x01 genPkt.addSubPkt(0x2, 0, 0x0228, 0x1, 10, data) From ca434eef06af6933908be7d281b3b79453495c9e Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 27 Jun 2025 09:43:53 +0800 Subject: [PATCH 29/41] =?UTF-8?q?smUnit=E7=9A=84fifo=E6=96=AD=E8=A8=80?= =?UTF-8?q?=E5=8F=98=E4=B8=BA=E6=9D=A1=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SMUnit.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala index befeb8e..dd51fcb 100644 --- a/src/main/scala/backBoard/shin/SMUnit.scala +++ b/src/main/scala/backBoard/shin/SMUnit.scala @@ -48,14 +48,14 @@ abstract class SMUnitBase(depth: Int = 4) extends Module { val isEmpty = ( wPtr === rPtr ) - when( io.enq ){ + when( io.enq & ~isFull ){ wPtr := wPtr + 1.U - assert( ~isFull) + // assert( ~isFull) } - when( io.deq ){ + when( io.deq & ~isEmpty ){ rPtr := rPtr + 1.U - assert( ~isEmpty ) + // assert( ~isEmpty ) } for( i <- 0 until depth ){ From 89c9ced39c1fde66adf53a9aa64d11a56f0accd2 Mon Sep 17 00:00:00 2001 From: bacon Date: Fri, 27 Jun 2025 15:11:49 +0800 Subject: [PATCH 30/41] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E4=BA=86=E6=B5=8B?= =?UTF-8?q?=E8=AF=95=E4=BB=A3=E7=A0=81=E4=B8=8A=E7=9A=84=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 975f7af..5b4b217 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -516,10 +516,6 @@ if __name__ == '__main__': genPkt.clean() genPkt.setPktType(0) - - - - #subPkt参数：索引、索引类型、地址、命令、长度、数据 genPkt.addSubPkt(0x0, 0, random.randint(0, 65535), 0xc, 12, b'\0'*12) @@ -1483,6 +1479,10 @@ if __name__ == '__main__': data[9] = 0x01 genPkt.addSubPkt(0x4, 0, 0x0228, 0x1, 10, data) + data = [0,] * 2 + data[0] = 0x80 + data[1] = 0x00 + genPkt.addSubPkt(0x0, 0, 0x302, 0xe, 2, data) gen_file_def = "ebmmu_tc6_settings" sm_idx = 0 From ba153dec2d359f62edf60346cc28c2ef32cf22c4 Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 26 Jun 2025 19:02:38 +0800 Subject: [PATCH 31/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0ebmmu=20test=206,?= =?UTF-8?q?=E5=86=99=E5=85=A5=E7=9A=84=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 21 ++++++- tb/shinTest/gen_pkt.py | 124 +++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+), 2 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 580c433..0b31fb5 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -25,7 +25,8 @@ //`define ENABLE_EBMMU_TC2_TEST //`define ENABLE_EBMMU_TC3_TEST //`define ENABLE_EBMMU_TC4_TEST -`define ENABLE_EBMMU_TC5_TEST +//`define ENABLE_EBMMU_TC5_TEST +`define ENABLE_EBMMU_TC6_TEST module ShinTopSpiTb( @@ -1382,7 +1383,7 @@ initial begin begin:EBMMU_TC5_TEST _t_start = $realtime; #1000 - $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用4"); + $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用5"); $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); `include "ebmmu_tc4_settings.vh" @@ -1396,6 +1397,22 @@ initial begin end `endif +`ifdef ENABLE_EBMMU_TC6_TEST + begin:EBMMU_TC6_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用6"); + $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); + + `include "ebmmu_tc6_settings.vh" + + `include "ebmmu_tc6_write.vh" + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end +`endif + #1000000 $display("Testcase Finished! Time Out !!!"); $fclose(spidata_file); diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 6809c54..83847d6 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1398,3 +1398,127 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + #-------------------------------------------------------------------------- + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU,测试用例6 + genPkt.clean() + genPkt.setPktType(0) + + addr_off = 0x58 + 0x80 + 0x98 + 0x81 + 0x8c + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + addr = addr_off + 0x0 + #print(hex(addr)) + data[0] = (addr & 0xff) + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x02 + data[9] = 0x01 + genPkt.addSubPkt(0x2, 0, 0x0228, 0x1, 10, data) + + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x4, 0, 0x0228, 0x1, 10, data) + + + gen_file_def = "ebmmu_tc6_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 0x80 * 4 + for i in range(0x80 * 4): + data[i] = i & 0xff + + genPkt.addSubPkt(0x1000, 2, addr_off, 0x1, 0x80 * 4, data) + + gen_file_def = "ebmmu_tc6_write" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + +genSlvSMReadData(1, 0, 0x80) + +genSlvSMReadData(2, 0, 0x80) + +genSlvSMReadData(3, 0, 0x80) + +genSlvSMReadData(4, 0, 0x80)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + From 79c3364492a55e27e5e6a13582d920922d98195b Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 30 Jun 2025 15:11:29 +0800 Subject: [PATCH 32/41] =?UTF-8?q?=E4=BF=AE=E5=A4=8Daddrw=E5=9C=A8=E9=80=BB?= =?UTF-8?q?=E8=BE=91=E5=AF=BB=E5=9D=80=E4=B8=8B=E7=9A=84=E6=93=8D=E4=BD=9C?= =?UTF-8?q?=E9=80=BB=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 52 +++++++++---------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 03aeb67..d91c21e 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -562,30 +562,30 @@ trait SlaveParserRW{ this: SlaveParserBase => logicAddrwNext := logicAddrw } - - when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填 - when( - ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | - ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) - ){ //常规寻址 + when( + ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ){ //常规寻址 + when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填 addrw := downRecParser.io.subMsgHeadReq.bits.address - } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){ //逻辑寻址 - addrw := acquireDownPhyAddrw - } - } .elsewhen( isWrite & downRecParser.io.data.fire ){ - when( - ( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) | - ( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) - ){ + } .elsewhen( isWrite & downRecParser.io.data.fire ){ addrw := addrw + 1.U - } .elsewhen( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ){ - addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U ) } + } .elsewhen( isDownLgcAddrwAcquireTrans & ( + ( downRecParser.io.subMsgHeadReq.fire & (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ) | + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + )){ + addrw := acquireDownPhyAddrw + } .elsewhen( + isWrite & downRecParser.io.data.fire & ( + ( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) | + ( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex ) + ) ){ + assert(~isDownLgcAddrwAcquireTrans) + addrw := Mux( downTransLenCnt === 0.U, 0.U, addrw + 1.U ) } - - - io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire io.lvds.dataw := downRecParser.io.data.bits @@ -731,14 +731,12 @@ trait SlaveParserRW{ this: SlaveParserBase => } .elsewhen(isLvdsEnR){ addrr := addrr + 1.U } - } .elsewhen( isUpLgcAddrrAcquireTrans ){ - when( - (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | - ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | - (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) - ){ - addrr := acquireUpPhyAddrr - } + } .elsewhen( isUpLgcAddrrAcquireTrans & ( + (upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) | + ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | + (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) + )){ + addrr := acquireUpPhyAddrr } .elsewhen( isLvdsEnR & ( ( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) | (~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex )) From efc334be9d155ef23c6a1dff3b0c3d1c2a9c3b85 Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 2 Jul 2025 11:34:47 +0800 Subject: [PATCH 33/41] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B=E4=B8=AD=E7=9A=84=E6=95=B0=E6=8D=AE?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 5b4b217..4d8a9ea 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1502,7 +1502,14 @@ if __name__ == '__main__': #subPkt参数：索引、索引类型、地址、命令、长度、数据 data = [0,] * 0x80 * 4 for i in range(0x80 * 4): - data[i] = i & 0xff + if i < 0x80: + data[i] = i & 0xff + elif i < 0x80+0x80: + data[i] = (i + 2 - 0x80) & 0xff + elif i < 0x80+0x80+0x80: + data[i] = (i + 3 - 0x80 - 0x80) & 0xff + else: + data[i] = (i + 5 - 0x80 - 0x80 - 0x80) & 0xff genPkt.addSubPkt(0x1000, 2, addr_off, 0x1, 0x80 * 4, data) From 9e77f9b0e5a3d38a7a40175fe73041cb639bf2ed Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 2 Jul 2025 14:01:53 +0800 Subject: [PATCH 34/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E6=96=B0=E7=9A=84ebmmu?= =?UTF-8?q?=E5=86=99=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 17 +++++ tb/shinTest/gen_pkt.py | 135 +++++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 0b31fb5..efdbe79 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -27,6 +27,7 @@ //`define ENABLE_EBMMU_TC4_TEST //`define ENABLE_EBMMU_TC5_TEST `define ENABLE_EBMMU_TC6_TEST +`define ENABLE_EBMMU_TC7_TEST module ShinTopSpiTb( @@ -1413,6 +1414,22 @@ initial begin end `endif +`ifdef ENABLE_EBMMU_TC7_TEST + begin:EBMMU_TC7_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例： ebmmu 测试用7"); + $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); + + `include "ebmmu_tc7_settings.vh" + + `include "ebmmu_tc7_write.vh" + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end +`endif + #1000000 $display("Testcase Finished! Time Out !!!"); $fclose(spidata_file); diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 4d8a9ea..0aed2dc 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1527,5 +1527,140 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) +#-------------------------------------------------------------------------- + #------------------------------------------------------------------------- + #>>>>>>设置EB-MMU,测试用例7 + genPkt.clean() + genPkt.setPktType(0) + + addr_off = 0x58 + 0x80 + 0x98 + 0x81 + 0x8c + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 30 + + addr = addr_off + 0x0 + #print(hex(addr)) + data[0] = (addr & 0xff) + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + + genPkt.addSubPkt(0x1, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x00 + genPkt.addSubPkt(0x2, 0, 0x0228, 0x1, 10, data) + + + data = [0,] * 30 + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x01 + genPkt.addSubPkt(0x3, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 30 + + addr = addr + 0x80 + #print(hex(addr)) + data[0] = (addr) & 0xff + data[1] = (addr >> 8) & 0xff + data[2] = 0x00 + data[3] = 0x10 + + data[4] = 0x00 + data[5] = 0x08 + + data[6] = 0x80 + data[7] = 0x00 + + data[8] = 0x03 + data[9] = 0x00 + genPkt.addSubPkt(0x4, 0, 0x0228, 0x1, 10, data) + + data = [0,] * 2 + data[0] = 0x80 + data[1] = 0x00 + genPkt.addSubPkt(0x0, 0, 0x302, 0xe, 2, data) + + gen_file_def = "ebmmu_tc7_settings" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + #------------------------------------------------------------------------- + #>>>>>>用EB-MMU方式读取EB-MMU设置 + genPkt.clean() + genPkt.setPktType(0) + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + data = [0,] * 0x80 * 4 + for i in range(0x80 * 4): + if i < 0x80: + data[i] = i & 0xff + elif i < 0x80+0x80: + data[i] = (i + 2 - 0x80) & 0xff + elif i < 0x80+0x80+0x80: + data[i] = (i + 3 - 0x80 - 0x80) & 0xff + else: + data[i] = (i + 5 - 0x80 - 0x80 - 0x80) & 0xff + + genPkt.addSubPkt(0x1000, 2, addr_off, 0x1, 0x80 * 4, data) + + gen_file_def = "ebmmu_tc7_write" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + +genSlvSMReadData(1, 0, 0x80) + +genSlvSMReadData(2, 0, 0x80) + +genSlvSMReadData(3, 0, 0x80) + +genSlvSMReadData(4, 0, 0x80)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + + + From 41d5adbdaa721d73d5517e3857e7bb52b818f782 Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 2 Jul 2025 18:40:31 +0800 Subject: [PATCH 35/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E7=9C=8B=E9=97=A8?= =?UTF-8?q?=E7=8B=97=E6=B5=8B=E8=AF=95=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/ShinTopSpiTb.v | 29 +++++++++++++- tb/shinTest/gen_pkt.py | 77 +++++++++++++++++++++++++++++++++++++- 2 files changed, 102 insertions(+), 4 deletions(-) diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index efdbe79..adfb873 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -26,8 +26,10 @@ //`define ENABLE_EBMMU_TC3_TEST //`define ENABLE_EBMMU_TC4_TEST //`define ENABLE_EBMMU_TC5_TEST -`define ENABLE_EBMMU_TC6_TEST -`define ENABLE_EBMMU_TC7_TEST +//`define ENABLE_EBMMU_TC6_TEST +//`define ENABLE_EBMMU_TC7_TEST + +`define ENABLE_WD_TC1_TEST module ShinTopSpiTb( @@ -792,6 +794,15 @@ initial begin spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(2)) ); spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(3)) ); spi_trans( (16'h70), (`SPI_READ), (4), (`IF_IDX(4)) ); + + $fdisplay(spidata_file, "-中断改为脉冲模式"); + txBuf[3] = 8'h10; + txBuf[4] = 8'h80; + spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(0)) ); + spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(1)) ); + spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(2)) ); + spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(3)) ); + spi_trans( (16'h7c), (`SPI_WRITE), (2), (`IF_IDX(4)) ); end `endif @@ -1430,6 +1441,20 @@ initial begin end `endif +`ifdef ENABLE_WD_TC1_TEST + begin:WD_TC7_TEST + _t_start = $realtime; + #1000 + $fdisplay(spidata_file, "\n\n测试用例： Watchdog 测试用1"); + $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp); + + `include "wd_tc1.vh" + + _t_end = $realtime; + $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start); + end +`endif + #1000000 $display("Testcase Finished! Time Out !!!"); $fclose(spidata_file); diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 0aed2dc..cd8361e 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -232,6 +232,25 @@ def genCheckInsertTimeCode(): + '''$fdisplay(spidata_file, "--检查时间戳插入");\n'''\ + '''spi_trans( (16'h24), (`SPI_READ), (2), (`IF_IDX(0)) ); //检查替换时间戳替换地址寄存器\n''' + +def genIFRwDataCode(dev, addr, isWrite = False, data_len=0, data = None): + if isWrite == True: + if (data == None) or (len(data) == 0): + data=list() + + code = '' + idx = 3 + for item in data: + code = code + '''txBuf[%d]=8'h%02x;\n'''%(idx, item & 0xff) + idx = idx + 1 + + code = code + '''spi_trans( (16'h%04x), (`SPI_WRITE), (%d), (`IF_IDX(%d)) );\n'''%(addr, data_len, dev) + return code + else: + code = '' + code = code + '''spi_trans( (16'h%04x), (`SPI_READ), (%d), (`IF_IDX(%d)) );\n'''%(addr, data_len, dev) + return code + def genSlvSMWriteData(dev, sm, data_len, data = None): smaddr = list() for i in range(8): @@ -1527,8 +1546,7 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) -#-------------------------------------------------------------------------- - #------------------------------------------------------------------------- + #-------------------------------------------------------------------------- #>>>>>>设置EB-MMU,测试用例7 genPkt.clean() genPkt.setPktType(0) @@ -1661,6 +1679,61 @@ if __name__ == '__main__': genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) + #-------------------------------------------------------------------------- + #>>>>>> 测试用例1 看门狗测试 + genPkt.clean() + genPkt.setPktType(0) + + data = 1<<1 ##使能看门狗1 + data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] + + data = 0x100 ##看门狗的超时值 + data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] + + data = 0xffffffff ##清除中断 + data2 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] + + genPkt.addBeforeExc( genIFRwDataCode(1, 0x404, True, 4, data0) + + genIFRwDataCode(1, 0x40C, True, 4, data1) + + genIFRwDataCode(1, 0x078, True, 4, data2) + + genIFRwDataCode(2, 0x078, True, 4, data2) + + genIFRwDataCode(3, 0x078, True, 4, data2) + + genIFRwDataCode(4, 0x078, True, 4, data2) + + genIFRwDataCode(1, 0x400, True, 4, [0xff, 0xff, 0xff, 0xff]) + + genIFRwDataCode(0, 0x074, False, 0x04) + + genIFRwDataCode(1, 0x074, False, 0x04) + + genIFRwDataCode(2, 0x074, False, 0x04) + + genIFRwDataCode(3, 0x074, False, 0x04) + + genIFRwDataCode(4, 0x074, False, 0x04) + + genIFRwDataCode(1, 0x400, False, 0x04)) + #genPkt.addBeforeExc( genIFRwDataCode(1, 0x078, True, 4, [0xff, 0xff, 0xff, 0xff])) + + data = [0,] * 2 + data[0] = 0x80 + data[1] = 0x00 + genPkt.addSubPkt(0x0, 0, 0x302, 0xe, 2, data) + + data = [0,] * 0x50 + + #subPkt参数：索引、索引类型、地址、命令、长度、数据 + genPkt.addSubPkt(1, 0, 0x800, 0x1, 0x50, data) + + gen_file_def = "wd_tc1" + sm_idx = 0 + + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx) + +genWriteTransPktCode(gen_file_def, sm_idx) + +genTrgTransPktCode(gen_file_def, sm_idx) + +genReadAckPktCode(gen_file_def, sm_idx) + +genIFRwDataCode(1, 0x800, False, 0x80) + +genIFRwDataCode(0, 0x074, False, 0x04) + +genIFRwDataCode(1, 0x074, False, 0x04) + +genIFRwDataCode(2, 0x074, False, 0x04) + +genIFRwDataCode(3, 0x074, False, 0x04) + +genIFRwDataCode(4, 0x074, False, 0x04) + +genIFRwDataCode(1, 0x400, False, 0x04)) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1) From bdea0fe7a84f14799e14dfca33039e2d333e362a Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 3 Jul 2025 09:35:45 +0800 Subject: [PATCH 36/41] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E7=9C=8B=E9=97=A8?= =?UTF-8?q?=E7=8B=97=E8=B6=85=E6=97=B6=E6=97=B6=E9=97=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index cd8361e..1e61792 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -1687,7 +1687,7 @@ if __name__ == '__main__': data = 1<<1 ##使能看门狗1 data0 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] - data = 0x100 ##看门狗的超时值 + data = 0x0010 ##看门狗的超时值 data1 = [data&0xff, (data>>8)&0xff, (data>>16)&0xff, (data>>24)&0xff] data = 0xffffffff ##清除中断 From 8211473d5ee236be700a01db68457f87a065370e Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 3 Jul 2025 10:50:51 +0800 Subject: [PATCH 37/41] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E7=9C=8B=E9=97=A8?= =?UTF-8?q?=E7=8B=97=E4=BD=BF=E8=83=BD=E7=BA=A6=E6=9D=9F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index c9244e9..bdbe97e 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -588,19 +588,19 @@ trait InterfaceMCUop{ this: InterfaceBase => for( i <- 0 until 8 ){ when( isEnW & addrw === "h400".U & dataw.extract(i) ){ wdtStatus(i) := false.B - } .elsewhen(io.wdtTrigger(i)){ + } .elsewhen(io.wdtTrigger(i) & cReg.wdtEnable.extract(i)){ wdtStatus(i) := true.B } when( isEnW & addrw === "h401".U & dataw.extract(i) ){ wdtStatus(8+i) := false.B - } .elsewhen(io.wdtTrigger(8+i)){ + } .elsewhen(io.wdtTrigger(8+i) & cReg.wdtEnable.extract(8+i)){ wdtStatus(8+i) := true.B } } for( i <- 0 until 1 ){ when( isEnW & addrw === "h402".U & dataw.extract(i) ){ wdtStatus(16+i) := false.B - } .elsewhen(io.wdtTrigger(16+i)){ + } .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){ wdtStatus(16+i) := true.B } } From 708c396d09c5a349e3c1593c4bc4737aa74a55d7 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 3 Jul 2025 11:42:15 +0800 Subject: [PATCH 38/41] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E7=A1=AC=E4=BB=B6?= =?UTF-8?q?=E9=94=99=E8=AF=AF=E6=B8=85=E7=90=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/ShinTop.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 0476b00..9f210f0 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -371,8 +371,8 @@ trait ShinTopSlave{ this: ShinTopBase => } - slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) - slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) + slaveParser.io.intHWClr(0) := interface.io.intHWClr(0) + slaveParser.io.intHWClr(1) := interface.io.intHWClr(1) interface.io.lvds <> slaveParser.io.lvds From 8569472a2a76a83265c1f084c5a121766699f98b Mon Sep 17 00:00:00 2001 From: bacon Date: Thu, 3 Jul 2025 14:45:05 +0800 Subject: [PATCH 39/41] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E7=94=9F=E6=88=90?= =?UTF-8?q?=E4=BB=A3=E7=A0=81=E5=8C=85=E9=95=BF=E7=9A=84=E6=A3=80=E6=9F=A5?= =?UTF-8?q?=E4=B8=8A=E9=99=90?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 1e61792..08a774e 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -51,7 +51,7 @@ class GenPkt(object): else: pkt_len = pkt_len + sp[5] + 8 - if pkt_len > 2048: + if pkt_len > 2044: print('Error, bad pkt_len:', pkt_len) return From 79d8a6999800e5c7ffe2c6455cf94e29c93fdacf Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 4 Jul 2025 11:02:10 +0800 Subject: [PATCH 40/41] =?UTF-8?q?=E4=BF=AE=E5=A4=8DrecParser=E7=9A=84?= =?UTF-8?q?=E8=AE=A1=E6=95=B0=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveRecParser.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index b5e04c9..78fbcc9 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -109,7 +109,8 @@ class SlaveRecParser extends Module{ frameLenCnt := 0.U } .elsewhen( ( stateCurr === STATE_SUBMSG_HEADER ) || - ( stateCurr === STATE_PAYLOAD_DATA ) + ( stateCurr === STATE_PAYLOAD_DATA ) || + ( stateCurr === STATE_SUBMSG_TAIL ) ){ frameLenCnt := frameLenCnt + 1.U } From 8bd861a72dfde1989992577dbbe5d69d62f555ac Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 4 Jul 2025 11:40:07 +0800 Subject: [PATCH 41/41] =?UTF-8?q?=E4=BF=AE=E5=A4=8D:=E5=8F=91=E9=80=81?= =?UTF-8?q?=E9=83=A8=E5=88=86=E5=A2=9E=E5=8A=A0=E5=AF=B9=E5=AD=90=E6=8A=A5?= =?UTF-8?q?=E6=96=87=E5=B0=BE=E7=9A=84CRC=E6=A0=A1=E9=AA=8C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveSendGen.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala index 8e43196..d121908 100644 --- a/src/main/scala/backBoard/shin/SlaveSendGen.scala +++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala @@ -53,7 +53,8 @@ class SlaveSendGen extends Module{ crc.io.isEnable := io.send.fire & ( stateCurr === STATE_FRAME_HEADER | stateCurr === STATE_SUBMSG_HEADER | - stateCurr === STATE_SUBMSG_DATA + stateCurr === STATE_SUBMSG_DATA | + stateCurr === STATE_SUBMSG_TAIL )