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不再通过crc校验来更新寄存器，还没等到crc火车已经回头开始上传，造成页面信息错误

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This commit is contained in:
RuigeLee
2024-04-14 17:44:59 +08:00
parent d810ca68e6
commit 1721d332ad
2 changed files with 18 additions and 14 deletions
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12
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -57,10 +57,14 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
downCnt := 0.U downCnt := 0.U
} }
when( lvdsSlv.io.downstream_rx_crc_valid ){ // when( lvdsSlv.io.downstream_rx_crc_valid ){
when( ~lvdsSlv.io.downstream_rx_crc_err ){ // when( ~lvdsSlv.io.downstream_rx_crc_err ){
downReg := downRegTemp // downReg := downRegTemp
} // }
// }
when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){
downReg := downRegTemp
} }
} }

20
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -249,18 +249,18 @@ with BackBoardSlvIn{
class BackBoardSlvOut16 extends BackBoardSlvLocal{ // class BackBoardSlvOut16 extends BackBoardSlvLocal{
val in = IO(Input(UInt(32.W))) // val in = IO(Input(UInt(32.W)))
val out = IO(Output(UInt(32.W))) // val out = IO(Output(UInt(32.W)))
val oe = IO(Output(UInt(32.W))) // val oe = IO(Output(UInt(32.W)))
out := Cat( (0 until 4).map{i => downReg(i)}.reverse ) // out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
oe := Cat( (4 until 8).map{i => downReg(i)}.reverse ) // oe := Cat( (4 until 8).map{i => downReg(i)}.reverse )
for( i <- 0 until 4 ) { // for( i <- 0 until 4 ) {
upReg(i) := in( i*8+7,8*i ) // upReg(i) := in( i*8+7,8*i )
} // }
} // }