From 1721d332ad914ddab42a488525b6b9b92c8de133 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sun, 14 Apr 2024 17:44:59 +0800 Subject: [PATCH] =?UTF-8?q?=E4=B8=8D=E5=86=8D=E9=80=9A=E8=BF=87crc?= =?UTF-8?q?=E6=A0=A1=E9=AA=8C=E6=9D=A5=E6=9B=B4=E6=96=B0=E5=AF=84=E5=AD=98?= =?UTF-8?q?=E5=99=A8=EF=BC=8C=E8=BF=98=E6=B2=A1=E7=AD=89=E5=88=B0crc?= =?UTF-8?q?=E7=81=AB=E8=BD=A6=E5=B7=B2=E7=BB=8F=E5=9B=9E=E5=A4=B4=E5=BC=80?= =?UTF-8?q?=E5=A7=8B=E4=B8=8A=E4=BC=A0=EF=BC=8C=E9=80=A0=E6=88=90=E9=A1=B5?= =?UTF-8?q?=E9=9D=A2=E4=BF=A1=E6=81=AF=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/BackBoardSlv.scala | 12 +++++++---- src/main/scala/backBoard/LocalRegisters.scala | 20 +++++++++---------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala index 43ce0f6..12151de 100644 --- a/src/main/scala/backBoard/BackBoardSlv.scala +++ b/src/main/scala/backBoard/BackBoardSlv.scala @@ -57,10 +57,14 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase => downCnt := 0.U } - when( lvdsSlv.io.downstream_rx_crc_valid ){ - when( ~lvdsSlv.io.downstream_rx_crc_err ){ - downReg := downRegTemp - } + // when( lvdsSlv.io.downstream_rx_crc_valid ){ + // when( ~lvdsSlv.io.downstream_rx_crc_err ){ + // downReg := downRegTemp + // } + // } + + when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){ + downReg := downRegTemp } } diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index ca98ed9..ae7c3c8 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -249,18 +249,18 @@ with BackBoardSlvIn{ -class BackBoardSlvOut16 extends BackBoardSlvLocal{ - val in = IO(Input(UInt(32.W))) - val out = IO(Output(UInt(32.W))) - val oe = IO(Output(UInt(32.W))) +// class BackBoardSlvOut16 extends BackBoardSlvLocal{ +// val in = IO(Input(UInt(32.W))) +// val out = IO(Output(UInt(32.W))) +// val oe = IO(Output(UInt(32.W))) - out := Cat( (0 until 4).map{i => downReg(i)}.reverse ) - oe := Cat( (4 until 8).map{i => downReg(i)}.reverse ) +// out := Cat( (0 until 4).map{i => downReg(i)}.reverse ) +// oe := Cat( (4 until 8).map{i => downReg(i)}.reverse ) - for( i <- 0 until 4 ) { - upReg(i) := in( i*8+7,8*i ) - } -} +// for( i <- 0 until 4 ) { +// upReg(i) := in( i*8+7,8*i ) +// } +// }