diff --git a/src/main/scala/backBoard/BackBoardSlv.scala b/src/main/scala/backBoard/BackBoardSlv.scala
index 43ce0f6..12151de 100644
--- a/src/main/scala/backBoard/BackBoardSlv.scala
+++ b/src/main/scala/backBoard/BackBoardSlv.scala
@@ -57,10 +57,14 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
     downCnt := 0.U
   }
 
-  when( lvdsSlv.io.downstream_rx_crc_valid ){
-    when( ~lvdsSlv.io.downstream_rx_crc_err ){
-      downReg := downRegTemp
-    }
+  // when( lvdsSlv.io.downstream_rx_crc_valid ){
+  //   when( ~lvdsSlv.io.downstream_rx_crc_err ){
+  //     downReg := downRegTemp
+  //   }
+  // }
+
+  when( RegNext(lvdsSlv.io.downstream_rx_data_valid,false.B) & ~lvdsSlv.io.downstream_rx_data_valid ){
+    downReg := downRegTemp
   }
 
 }
diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index ca98ed9..ae7c3c8 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -249,18 +249,18 @@ with BackBoardSlvIn{
 
 
 
-class BackBoardSlvOut16 extends BackBoardSlvLocal{
-  val in  = IO(Input(UInt(32.W)))
-  val out = IO(Output(UInt(32.W)))
-  val oe  = IO(Output(UInt(32.W)))
+// class BackBoardSlvOut16 extends BackBoardSlvLocal{
+//   val in  = IO(Input(UInt(32.W)))
+//   val out = IO(Output(UInt(32.W)))
+//   val oe  = IO(Output(UInt(32.W)))
 
 
 
-  out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
-  oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )
+//   out := Cat( (0 until 4).map{i => downReg(i)}.reverse )
+//   oe  := Cat( (4 until 8).map{i => downReg(i)}.reverse )
 
-  for( i <- 0 until 4 ) {
-    upReg(i) := in( i*8+7,8*i )
-  }
-}
+//   for( i <- 0 until 4 ) {
+//     upReg(i) := in( i*8+7,8*i )
+//   }
+// }