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rplTimeStampTx寄存器在发送完成后清零，优先级最高

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This commit is contained in:
Ruige Lee
2025-05-29 10:28:41 +08:00
parent f09cc0cb0e
commit 14832ac770
1 changed files with 9 additions and 6 deletions
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15
src/main/scala/backBoard/shin/Interface.scala
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@@ -473,14 +473,17 @@ trait InterfaceMCUop{ this: InterfaceBase =>
cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) ) cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) )
} }
val rplTimeStampTx = RegInit(0.U(16.W))
mReg.rplTimeStampTx := rplTimeStampTx
when( io.intMstTrig(0) ){
mReg.rplTimeStampTx := rplTimeStampTx := rplTimeStampTx & "h3FFF".U(16.W)
Cat( } .elsewhen( isEnW & addrw === "h25".U ){
RegEnable( dataw, 0.U, isEnW & addrw === "h25".U ), rplTimeStampTx := Cat( dataw, rplTimeStampTx(7,0) )
RegEnable( dataw, 0.U, isEnW & addrw === "h24".U ) } .elsewhen( isEnW & addrw === "h24".U ){
) rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw )
}
when( isEnW & isSlvMode ){ when( isEnW & isSlvMode ){