diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index c1ec329..41c20dd 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -473,14 +473,17 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) )
   }
 
+  val rplTimeStampTx = RegInit(0.U(16.W))
 
+  mReg.rplTimeStampTx := rplTimeStampTx
 
-
-  mReg.rplTimeStampTx := 
-    Cat(
-      RegEnable( dataw, 0.U, isEnW & addrw === "h25".U ),
-      RegEnable( dataw, 0.U, isEnW & addrw === "h24".U )
-    )
+  when( io.intMstTrig(0) ){
+    rplTimeStampTx := rplTimeStampTx & "h3FFF".U(16.W)
+  } .elsewhen( isEnW & addrw === "h25".U ){
+    rplTimeStampTx := Cat( dataw, rplTimeStampTx(7,0) )
+  } .elsewhen( isEnW & addrw === "h24".U ){
+    rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw )
+  }
 
 
   when( isEnW & isSlvMode ){