From 14832ac770f978f2f50a944d50aa3f64e87dc064 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 29 May 2025 10:28:41 +0800
Subject: [PATCH] =?UTF-8?q?rplTimeStampTx=E5=AF=84=E5=AD=98=E5=99=A8?=
 =?UTF-8?q?=E5=9C=A8=E5=8F=91=E9=80=81=E5=AE=8C=E6=88=90=E5=90=8E=E6=B8=85?=
 =?UTF-8?q?=E9=9B=B6=EF=BC=8C=E4=BC=98=E5=85=88=E7=BA=A7=E6=9C=80=E9=AB=98?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index c1ec329..41c20dd 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -473,14 +473,17 @@ trait InterfaceMCUop{ this: InterfaceBase =>
     cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U(16.W) + i.U)) )
   }
 
+  val rplTimeStampTx = RegInit(0.U(16.W))
 
+  mReg.rplTimeStampTx := rplTimeStampTx
 
-
-  mReg.rplTimeStampTx := 
-    Cat(
-      RegEnable( dataw, 0.U, isEnW & addrw === "h25".U ),
-      RegEnable( dataw, 0.U, isEnW & addrw === "h24".U )
-    )
+  when( io.intMstTrig(0) ){
+    rplTimeStampTx := rplTimeStampTx & "h3FFF".U(16.W)
+  } .elsewhen( isEnW & addrw === "h25".U ){
+    rplTimeStampTx := Cat( dataw, rplTimeStampTx(7,0) )
+  } .elsewhen( isEnW & addrw === "h24".U ){
+    rplTimeStampTx := Cat(rplTimeStampTx(15,8), dataw )
+  }
 
 
   when( isEnW & isSlvMode ){