CDR基本测试通过

tb/cdrInOut_tb.v

@@ -0,0 +1,137 @@
+`timescale 1 ns / 1 ps
+
+
+module CDRInOut_tb();
+
+
+
+
+    reg clock = 0;
+    reg reset = 1;
+
+    reg overCLK = 0;
+
+    wire serDat;
+
+    wire      tx_axis_ready;
+
+    reg       tx_axis_valid = 0;
+    reg [7:0] tx_axis_bits_tdata;
+    reg       tx_axis_bits_tlast;
+    reg       tx_axis_bits_tuser;
+
+
+
+    reg        rx_axis_ready = 1;
+    wire       rx_axis_valid;
+    wire [7:0] rx_axis_bits_tdata;
+    wire       rx_axis_bits_tlast;
+    wire       rx_axis_bits_tuser;
+
+
+
+    CDRIn s_CDRIn(
+        .clock(clock),
+        .reset(reset),
+
+        .io_axis_ready(rx_axis_ready),
+        .io_axis_valid(rx_axis_valid),
+        .io_axis_bits_tdata(rx_axis_bits_tdata),
+        .io_axis_bits_tlast(rx_axis_bits_tlast),
+        .io_axis_bits_tuser(rx_axis_bits_tuser),
+
+        .io_serDat(serDat),
+        .io_overCLK(overCLK)
+    );
+
+
+
+
+
+
+
+
+    CDROut s_CDROut(
+    .clock(clock),
+    .reset(reset),
+
+    .io_axis_ready(tx_axis_ready),
+    .io_axis_valid(tx_axis_valid),
+    .io_axis_bits_tdata(tx_axis_bits_tdata),
+    .io_axis_bits_tlast(tx_axis_bits_tlast),
+    .io_axis_bits_tuser(tx_axis_bits_tuser),
+    .io_serDat(serDat)
+    );
+
+
+
+
+
+initial begin
+    forever #80 clock = ~clock;
+end
+
+initial begin
+    forever #20 overCLK = ~overCLK;
+end
+
+initial begin
+    # 100 reset = 1;
+    # 100 reset = 0;
+end
+
+
+reg [7:0] cnt = 0;
+
+
+
+    always @(posedge clock) begin
+        if( reset ) begin
+            cnt <= #2 0;
+            tx_axis_valid <= #2 1'b0;
+        end else begin
+            if( cnt == 8'd0 ) begin
+                tx_axis_valid      <= #2 1'b1;
+                tx_axis_bits_tdata <= #2 0;
+                tx_axis_bits_tlast <= #2 1'b0;
+                tx_axis_bits_tuser <= #2 1'b0;
+                cnt <= #2 cnt + 8'd1;
+            end else begin
+                if( tx_axis_valid & tx_axis_ready ) begin
+                    if ( tx_axis_bits_tlast ) begin
+                        tx_axis_valid      <= #2 1'b0;
+                        tx_axis_bits_tlast <= #2 1'b0;
+                    end else begin
+                        tx_axis_bits_tdata <= #2 cnt;
+                        tx_axis_bits_tuser <= #2 1'b0;
+
+                        if( cnt == 8'd1 ) begin
+                            tx_axis_bits_tdata <= #2 32;
+                        end
+
+                        if( cnt == 8'd35 ) begin
+                            tx_axis_bits_tlast <= #2 1'b1;
+                        end else begin
+                            cnt <= #2 cnt + 8'd1;
+                        end
+                    end
+                end
+            end
+        end
+    end
+
+
+
+    initial begin
+        # 100000
+        $finish;
+
+    end
+
+    initial begin
+        $dumpfile("./build/wave.vcd"); //生成的vcd文件名称
+        $dumpvars(0, CDRInOut_tb);//tb模块名称
+    end
+
+
+endmodule