138 lines
2.7 KiB
Verilog
138 lines
2.7 KiB
Verilog
`timescale 1 ns / 1 ps
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module CDRInOut_tb();
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reg clock = 0;
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reg reset = 1;
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reg overCLK = 0;
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wire serDat;
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wire tx_axis_ready;
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reg tx_axis_valid = 0;
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reg [7:0] tx_axis_bits_tdata;
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reg tx_axis_bits_tlast;
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reg tx_axis_bits_tuser;
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reg rx_axis_ready = 1;
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wire rx_axis_valid;
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wire [7:0] rx_axis_bits_tdata;
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wire rx_axis_bits_tlast;
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wire rx_axis_bits_tuser;
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CDRIn s_CDRIn(
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.clock(clock),
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.reset(reset),
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.io_axis_ready(rx_axis_ready),
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.io_axis_valid(rx_axis_valid),
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.io_axis_bits_tdata(rx_axis_bits_tdata),
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.io_axis_bits_tlast(rx_axis_bits_tlast),
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.io_axis_bits_tuser(rx_axis_bits_tuser),
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.io_serDat(serDat),
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.io_overCLK(overCLK)
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);
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CDROut s_CDROut(
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.clock(clock),
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.reset(reset),
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.io_axis_ready(tx_axis_ready),
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.io_axis_valid(tx_axis_valid),
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.io_axis_bits_tdata(tx_axis_bits_tdata),
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.io_axis_bits_tlast(tx_axis_bits_tlast),
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.io_axis_bits_tuser(tx_axis_bits_tuser),
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.io_serDat(serDat)
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);
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initial begin
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forever #80 clock = ~clock;
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end
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initial begin
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forever #20 overCLK = ~overCLK;
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end
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initial begin
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# 100 reset = 1;
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# 100 reset = 0;
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end
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reg [7:0] cnt = 0;
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always @(posedge clock) begin
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if( reset ) begin
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cnt <= #2 0;
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tx_axis_valid <= #2 1'b0;
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end else begin
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if( cnt == 8'd0 ) begin
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tx_axis_valid <= #2 1'b1;
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tx_axis_bits_tdata <= #2 0;
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tx_axis_bits_tlast <= #2 1'b0;
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tx_axis_bits_tuser <= #2 1'b0;
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cnt <= #2 cnt + 8'd1;
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end else begin
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if( tx_axis_valid & tx_axis_ready ) begin
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if ( tx_axis_bits_tlast ) begin
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tx_axis_valid <= #2 1'b0;
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tx_axis_bits_tlast <= #2 1'b0;
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end else begin
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tx_axis_bits_tdata <= #2 cnt;
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tx_axis_bits_tuser <= #2 1'b0;
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if( cnt == 8'd1 ) begin
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tx_axis_bits_tdata <= #2 32;
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end
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if( cnt == 8'd35 ) begin
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tx_axis_bits_tlast <= #2 1'b1;
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end else begin
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cnt <= #2 cnt + 8'd1;
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end
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end
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end
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end
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end
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end
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initial begin
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# 100000
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$finish;
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end
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initial begin
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$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
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$dumpvars(0, CDRInOut_tb);//tb模块名称
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end
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endmodule
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