diff --git a/.gitignore b/.gitignore index d35bf55..f6b81fa 100644 --- a/.gitignore +++ b/.gitignore @@ -346,3 +346,6 @@ generated/ project/.bloop/riscv-mac-swich-build.json src/main/scala/mac/MacTilelink.scala doc/ +tb/CDRIn.v +tb/CDROut.v +tb/crc32_8.v diff --git a/Makefile b/Makefile index 094d19e..35797eb 100644 --- a/Makefile +++ b/Makefile @@ -117,13 +117,15 @@ VSimBack: tb: + cp ./generated/cdr/crc32_8.v ./tb + cp ./generated/cdr/CDRIn.v ./tb cp ./generated/cdr/CDROut.v ./tb iverilog -Wall \ -o ./build/wave.iverilog \ -y ./tb \ -I ./tb \ -D RANDOMIZE_REG_INIT \ - ./tb/cdrOut_tb.v + ./tb/cdrInOut_tb.v vvp -N ./build/wave.iverilog -lxt2 vcd: diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index ed8116a..c8f12b0 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -53,7 +53,7 @@ trait CDRInAxis{ this: CDRInBase => val crcCmp = Reg(UInt(32.W)) val bitCnt = Reg(UInt(3.W)) - val byteCnt = Reg(UInt(16.W)) + val byteCnt = RegInit(0.U(16.W)) val syncSerDat: Bool val shiftData = RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat) @@ -66,10 +66,10 @@ trait CDRInAxis{ this: CDRInBase => stateNext := Mux1H(Seq( - (stateCurr === STATE_IDLE) -> ( Mux( (byteCnt === 8.U) & (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE - (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ), - (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD - (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 4.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC + (stateCurr === STATE_IDLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 7.U) & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE + (stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ), + (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD + (stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC )) @@ -88,17 +88,17 @@ trait CDRInAxis{ this: CDRInBase => byteCnt := 1.U } .elsewhen( bitCnt === 7.U ){ when( stateCurr === STATE_IDLE ){ - byteCnt := Mux( byteCnt =/= 8.U & shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass - assert( byteCnt <= 8.U ) + byteCnt := Mux( byteCnt =/= 7.U & shiftData === ETH_PRE, byteCnt + 1.U, 0.U)//keep align, align failed or SFD pass + assert( byteCnt <= 7.U ) } .elsewhen( stateCurr === STATE_HEADER ){ - byteCnt := Mux( byteCnt =/= (HeaderByte).U, byteCnt + 1.U, 0.U ) - assert( byteCnt <= (HeaderByte).U ) + byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U ) + assert( byteCnt <= (HeaderByte-1).U ) } .elsewhen( stateCurr === STATE_PAYLOAD ){ - byteCnt := Mux( byteCnt =/= payloadLen, byteCnt + 1.U, 0.U ) - assert( byteCnt <= payloadLen ) + byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U ) + assert( byteCnt <= ( payloadLen-1.U ) ) } .elsewhen( stateCurr === STATE_CRC ){ - byteCnt := Mux( byteCnt =/= 4.U, byteCnt + 1.U, 0.U ) - assert( byteCnt <= 4.U ) + byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U ) + assert( byteCnt <= 3.U ) } } @@ -110,8 +110,8 @@ trait CDRInAxis{ this: CDRInBase => val axis_valid = RegInit(false.B) val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ) - val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 4.U & (crcOut =/= ~Cat( crcCmp(23,0), shiftData )), bitCnt === 7.U ) - val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 4.U, bitCnt === 7.U ) + val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 7.U ) + val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 7.U ) io.axis.valid := axis_valid io.axis.bits.tdata := axis_tdata @@ -126,7 +126,7 @@ trait CDRInAxis{ this: CDRInBase => } when( stateCurr === STATE_CRC & bitCnt === 7.U ){ - crcCmp := Cat( crcCmp(23,0), shiftData ) + crcCmp := Cat( shiftData, crcCmp(31,8) ) } diff --git a/src/test/scala/gcd/test.scala b/src/test/scala/gcd/test.scala index e9b7a10..3f34733 100644 --- a/src/test/scala/gcd/test.scala +++ b/src/test/scala/gcd/test.scala @@ -38,11 +38,11 @@ object testModule extends App { )) - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq( + (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( ChiselGeneratorAnnotation(() => { new CDROut }) )) - (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-E", "verilog" ) ++ args, Seq( + (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/cdr/", "-e", "verilog" ) ++ args, Seq( ChiselGeneratorAnnotation(() => { new CDRIn }) )) diff --git a/tb/cdrInOut_tb.v b/tb/cdrInOut_tb.v new file mode 100644 index 0000000..a83d8f3 --- /dev/null +++ b/tb/cdrInOut_tb.v @@ -0,0 +1,137 @@ +`timescale 1 ns / 1 ps + + +module CDRInOut_tb(); + + + + + reg clock = 0; + reg reset = 1; + + reg overCLK = 0; + + wire serDat; + + wire tx_axis_ready; + + reg tx_axis_valid = 0; + reg [7:0] tx_axis_bits_tdata; + reg tx_axis_bits_tlast; + reg tx_axis_bits_tuser; + + + + reg rx_axis_ready = 1; + wire rx_axis_valid; + wire [7:0] rx_axis_bits_tdata; + wire rx_axis_bits_tlast; + wire rx_axis_bits_tuser; + + + + CDRIn s_CDRIn( + .clock(clock), + .reset(reset), + + .io_axis_ready(rx_axis_ready), + .io_axis_valid(rx_axis_valid), + .io_axis_bits_tdata(rx_axis_bits_tdata), + .io_axis_bits_tlast(rx_axis_bits_tlast), + .io_axis_bits_tuser(rx_axis_bits_tuser), + + .io_serDat(serDat), + .io_overCLK(overCLK) + ); + + + + + + + + + CDROut s_CDROut( + .clock(clock), + .reset(reset), + + .io_axis_ready(tx_axis_ready), + .io_axis_valid(tx_axis_valid), + .io_axis_bits_tdata(tx_axis_bits_tdata), + .io_axis_bits_tlast(tx_axis_bits_tlast), + .io_axis_bits_tuser(tx_axis_bits_tuser), + .io_serDat(serDat) + ); + + + + + +initial begin + forever #80 clock = ~clock; +end + +initial begin + forever #20 overCLK = ~overCLK; +end + +initial begin + # 100 reset = 1; + # 100 reset = 0; +end + + +reg [7:0] cnt = 0; + + + + always @(posedge clock) begin + if( reset ) begin + cnt <= #2 0; + tx_axis_valid <= #2 1'b0; + end else begin + if( cnt == 8'd0 ) begin + tx_axis_valid <= #2 1'b1; + tx_axis_bits_tdata <= #2 0; + tx_axis_bits_tlast <= #2 1'b0; + tx_axis_bits_tuser <= #2 1'b0; + cnt <= #2 cnt + 8'd1; + end else begin + if( tx_axis_valid & tx_axis_ready ) begin + if ( tx_axis_bits_tlast ) begin + tx_axis_valid <= #2 1'b0; + tx_axis_bits_tlast <= #2 1'b0; + end else begin + tx_axis_bits_tdata <= #2 cnt; + tx_axis_bits_tuser <= #2 1'b0; + + if( cnt == 8'd1 ) begin + tx_axis_bits_tdata <= #2 32; + end + + if( cnt == 8'd35 ) begin + tx_axis_bits_tlast <= #2 1'b1; + end else begin + cnt <= #2 cnt + 8'd1; + end + end + end + end + end + end + + + + initial begin + # 100000 + $finish; + + end + + initial begin + $dumpfile("./build/wave.vcd"); //生成的vcd文件名称 + $dumpvars(0, CDRInOut_tb);//tb模块名称 + end + + +endmodule