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增加输出模块的的错误输入

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RuigeLee
2024-05-08 09:32:34 +08:00
parent a6f376f21d
commit 0eb7e7b15b
1 changed files with 6 additions and 1 deletions
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7
src/main/scala/backBoard/LocalRegisters.scala
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@@ -251,6 +251,7 @@ class DOut16 extends BackBoardSlvLocal
with BackBoardSlvStatusPR with BackBoardSlvStatusPR
with BackBoardSlvOut16{ with BackBoardSlvOut16{
val out = IO(Output(UInt(16.W))) val out = IO(Output(UInt(16.W)))
val flt = IO(Input(Vec(2, Bool())))
when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
outReg := Cat(downRegTemp(3), downRegTemp(2)) outReg := Cat(downRegTemp(3), downRegTemp(2))
@@ -267,7 +268,11 @@ with BackBoardSlvOut16{
upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } ) upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } )
} }
chsWire := 0.U.asTypeOf(chsWire) for( i <- 0 until 8 ){
chsWire(i) := Mux( flt(0) === true.B, "b00".U, "b01".U)
chsWire(8+i) := Mux( flt(1) === true.B, "b00".U, "b01".U)
}
out := outPin out := outPin