diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index ba90899..49e1e85 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -251,6 +251,7 @@ class DOut16 extends BackBoardSlvLocal
 with BackBoardSlvStatusPR
 with BackBoardSlvOut16{
   val out = IO(Output(UInt(16.W)))
+  val flt = IO(Input(Vec(2, Bool())))
 
   when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
     outReg := Cat(downRegTemp(3), downRegTemp(2))
@@ -267,7 +268,11 @@ with BackBoardSlvOut16{
     upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } )
   }
 
-  chsWire := 0.U.asTypeOf(chsWire)
+  for( i <- 0 until 8 ){
+    chsWire(i)   := Mux( flt(0) === true.B, "b00".U, "b01".U)
+    chsWire(8+i) := Mux( flt(1) === true.B, "b00".U, "b01".U)
+  }
+
   out := outPin