From 0eb7e7b15be53524b103169eeb463f611c3b73df Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 8 May 2024 09:32:34 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E8=BE=93=E5=87=BA=E6=A8=A1?= =?UTF-8?q?=E5=9D=97=E7=9A=84=E7=9A=84=E9=94=99=E8=AF=AF=E8=BE=93=E5=85=A5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/LocalRegisters.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index ba90899..49e1e85 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -251,6 +251,7 @@ class DOut16 extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvOut16{ val out = IO(Output(UInt(16.W))) + val flt = IO(Input(Vec(2, Bool()))) when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){ outReg := Cat(downRegTemp(3), downRegTemp(2)) @@ -267,7 +268,11 @@ with BackBoardSlvOut16{ upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } ) } - chsWire := 0.U.asTypeOf(chsWire) + for( i <- 0 until 8 ){ + chsWire(i) := Mux( flt(0) === true.B, "b00".U, "b01".U) + chsWire(8+i) := Mux( flt(1) === true.B, "b00".U, "b01".U) + } + out := outPin