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开放lvds对smtrigLen寄存器的写权限

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This commit is contained in:
Ruige Lee
2025-05-22 19:42:09 +08:00
parent 4834cf2029
commit 0e3178c9da
1 changed files with 24 additions and 5 deletions
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29
src/main/scala/backBoard/shin/Interface.scala
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@@ -537,12 +537,31 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
val dataw: UInt
val isEnR: Bool
val smTrigLen_H = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
val smTrigLen_L = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
for( i <- 0 until 8 ){
cReg.smTrigLen(i) :=
Cat(
RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
)
cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
when( isEnW & addrw === ("h303".U + (i*4).U) ){
smTrigLen_H(i) := dataw
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U + (i*4).U)){
smTrigLen_H(i) := io.lvds.dataw
}
when( isEnW & addrw === ("h302".U + (i*4).U) ){
smTrigLen_L(i) := dataw
} .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U + (i*4).U)){
smTrigLen_L(i) := io.lvds.dataw
}
// Cat(
// RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
// RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
// )
}