From 0e3178c9da29c19b704155ae0fe57b2037922ac4 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Thu, 22 May 2025 19:42:09 +0800
Subject: [PATCH] =?UTF-8?q?=E5=BC=80=E6=94=BElvds=E5=AF=B9smtrigLen?=
 =?UTF-8?q?=E5=AF=84=E5=AD=98=E5=99=A8=E7=9A=84=E5=86=99=E6=9D=83=E9=99=90?=
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---
 src/main/scala/backBoard/shin/Interface.scala | 29 +++++++++++++++----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index b6ffe99..987e742 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -537,12 +537,31 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   val dataw: UInt
   val isEnR: Bool
 
+
+  val smTrigLen_H = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
+  val smTrigLen_L = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
+
+
   for( i <- 0 until 8 ){
-    cReg.smTrigLen(i) := 
-      Cat(
-        RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
-      )
+    cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
+
+    when( isEnW & addrw === ("h303".U + (i*4).U) ){
+      smTrigLen_H(i) := dataw
+    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U + (i*4).U)){
+      smTrigLen_H(i) := io.lvds.dataw
+    }
+
+    when( isEnW & addrw === ("h302".U + (i*4).U) ){
+      smTrigLen_L(i) := dataw
+    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U + (i*4).U)){
+      smTrigLen_L(i) := io.lvds.dataw
+    }
+
+
+      // Cat(
+      //   RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
+      //   RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
+      // )
 
   }