diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index b6ffe99..987e742 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -537,12 +537,31 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   val dataw: UInt
   val isEnR: Bool
 
+
+  val smTrigLen_H = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
+  val smTrigLen_L = for( i <- 0 until 8 ) yield { RegInit(0.U(8.W)) }
+
+
   for( i <- 0 until 8 ){
-    cReg.smTrigLen(i) := 
-      Cat(
-        RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
-      )
+    cReg.smTrigLen(i) := Cat( smTrigLen_H(i), smTrigLen_L(i) )
+
+    when( isEnW & addrw === ("h303".U + (i*4).U) ){
+      smTrigLen_H(i) := dataw
+    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h303".U + (i*4).U)){
+      smTrigLen_H(i) := io.lvds.dataw
+    }
+
+    when( isEnW & addrw === ("h302".U + (i*4).U) ){
+      smTrigLen_L(i) := dataw
+    } .elsewhen( io.lvds.isEnW & io.lvds.addrw === ("h302".U + (i*4).U)){
+      smTrigLen_L(i) := io.lvds.dataw
+    }
+
+
+      // Cat(
+      //   RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ),
+      //   RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ),
+      // )
 
   }