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修正解锁条件

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This commit is contained in:
Ruige Lee
2025-08-22 14:24:41 +08:00
parent 06996d6945
commit 0a0a7a7712
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -117,7 +117,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W )) val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
val isLock = RegInit(false.B) val isLock = RegInit(false.B)
when( sampleReg.reduce(_|_) === false.B ){ when( sampleReg_sync.reduce(_|_) === false.B ){
when( clearCnt =/= 10.U ){ when( clearCnt =/= 10.U ){
clearCnt := clearCnt + 1.U clearCnt := clearCnt + 1.U
} }
@@ -125,7 +125,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
clearCnt := 0.U clearCnt := 0.U
} }
when( sampleReg.reduce(_|_) === false.B ){ when( ~isLock ){
checkCnt := 0.U checkCnt := 0.U
} .otherwise{ } .otherwise{
checkCnt := checkCnt + 1.U checkCnt := checkCnt + 1.U