diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 374cf21..a9557f7 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -117,7 +117,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
   val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
   val isLock = RegInit(false.B)
 
-  when( sampleReg.reduce(_|_) === false.B ){
+  when( sampleReg_sync.reduce(_|_) === false.B ){
     when( clearCnt =/= 10.U ){
       clearCnt := clearCnt + 1.U
     }
@@ -125,7 +125,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
     clearCnt := 0.U
   }
 
-  when( sampleReg.reduce(_|_) === false.B ){
+  when( ~isLock ){
     checkCnt := 0.U
   } .otherwise{
     checkCnt := checkCnt + 1.U