From 0a0a7a771235859bec2a845bb506d387ede488a9 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 22 Aug 2025 14:24:41 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E8=A7=A3=E9=94=81=E6=9D=A1?= =?UTF-8?q?=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 374cf21..a9557f7 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -117,7 +117,7 @@ trait CDRInMultiSample{ this: CDRInBase => val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W )) val isLock = RegInit(false.B) - when( sampleReg.reduce(_|_) === false.B ){ + when( sampleReg_sync.reduce(_|_) === false.B ){ when( clearCnt =/= 10.U ){ clearCnt := clearCnt + 1.U } @@ -125,7 +125,7 @@ trait CDRInMultiSample{ this: CDRInBase => clearCnt := 0.U } - when( sampleReg.reduce(_|_) === false.B ){ + when( ~isLock ){ checkCnt := 0.U } .otherwise{ checkCnt := checkCnt + 1.U