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rx DMA编译完成

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This commit is contained in:
RuigeLee
2023-10-20 14:42:15 +08:00
parent c5f9b4d74f
commit 0215add0d4
8 changed files with 63 additions and 56 deletions
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2
src/main/scala/Switch/mac/MAC.scala
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@@ -31,7 +31,7 @@ class MacIO extends Bundle{
val mii = new MII
val cfg = Flipped(new Mac_Config_Bundle)
val rxEnq = new Receive_Enq_Bundle
val txDeq = Flipped(new Transmit_Deq_Bundle)
val txDeq = Flipped(new Transmit_Bundle)
// val int_o = Output(Bool())

4
src/main/scala/Switch/mac/MacTilelink.scala
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@@ -57,7 +57,7 @@ abstract class MacTileLinkBase() extends Module{
val rxEnq = new Receive_Enq_Bundle
val txDeq = Flipped(new Transmit_Deq_Bundle)
val txDeq = Flipped(new Transmit_Bundle)
}
@@ -164,7 +164,7 @@ abstract class MacTileLinkBase() extends Module{
val txRespValid = RegInit(false.B)
val txRespBits = Reg(new Transmit_Deq_Resp_Bundle)
val txRespBits = Reg(new Transmit_Resp_Bundle)
io.txDeq.resp.valid := txRespValid
io.txDeq.resp.bits := txRespBits