854 lines
27 KiB
Scala
854 lines
27 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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import Switch._
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class MII extends Bundle with MDIO{
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// Tx
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val mtx_clk_pad_i = Input(Bool())
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val mtxd_pad_o = Output(UInt(4.W))
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val mtxen_pad_o = Output(Bool())
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val mtxerr_pad_o = Output(Bool())
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// Rx
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val mrx_clk_pad_i = Input(Bool())
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val mrxd_pad_i = Input(UInt(4.W))
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val mrxdv_pad_i = Input(Bool())
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val mrxerr_pad_i = Input(Bool())
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// Common Tx and Rx
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val mcoll_pad_i = Input(Bool())
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val mcrs_pad_i = Input(Bool())
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}
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class MacIO extends Bundle{
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val mii = new MII
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val cfg = Flipped(new Mac_Config_Bundle)
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val rxEnq = new Receive_Enq_Bundle
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val txDeq = Flipped(new Transmit_Bundle)
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// val int_o = Output(Bool())
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val isLoopBack = Output(Bool())
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val asyncReset = Input(AsyncReset())
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}
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class Mac extends Module{
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val io = IO(new MacIO)
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val r_ClkDiv = Wire(UInt(8.W))
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val r_MiiNoPre = Wire(Bool())
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val r_CtrlData = Wire(UInt(16.W))
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val r_FIAD = Wire(UInt(5.W))
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val r_RGAD = Wire(UInt(5.W))
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val r_WCtrlData = Wire(Bool())
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val r_RStat = Wire(Bool())
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val r_ScanStat = Wire(Bool())
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val NValid_stat = Wire(Bool())
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val Busy_stat = Wire(Bool())
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val LinkFail = Wire(Bool())
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val Prsd = Wire(UInt(16.W))
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val WCtrlDataStart = Wire(Bool())
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val RStatStart = Wire(Bool())
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val UpdateMIIRX_DATAReg = Wire(Bool())
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dontTouch( r_ClkDiv )
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dontTouch( r_MiiNoPre )
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dontTouch( r_CtrlData )
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dontTouch( r_FIAD )
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dontTouch( r_RGAD )
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dontTouch( r_WCtrlData )
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dontTouch( r_RStat )
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dontTouch( r_ScanStat )
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dontTouch( NValid_stat )
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dontTouch( Busy_stat )
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dontTouch( LinkFail )
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dontTouch( Prsd )
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dontTouch( WCtrlDataStart )
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dontTouch( RStatStart )
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dontTouch( UpdateMIIRX_DATAReg )
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val TxStartFrm = Wire(Bool())
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val TxEndFrm = Wire(Bool())
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val TxUsedData = Wire(Bool())
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val TxData = Wire(UInt(8.W))
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val TxRetry = Wire(Bool())
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val TxAbort = Wire(Bool())
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val TxDone = Wire(Bool())
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val TPauseRq = Wire(Bool())
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dontTouch(TxStartFrm)
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dontTouch(TxEndFrm )
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dontTouch(TxUsedData)
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dontTouch(TxData )
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dontTouch(TxRetry )
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dontTouch(TxAbort )
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dontTouch(TxDone )
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dontTouch(TPauseRq )
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val RstTxPauseRq = RegInit(false.B)
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// Connecting Miim module
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val miim = Module(new MIIM)
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miim.io.Divider := r_ClkDiv
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miim.io.NoPre := r_MiiNoPre
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miim.io.WCtrlData := r_WCtrlData
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miim.io.CtrlData := r_CtrlData
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miim.io.Fiad := r_FIAD
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miim.io.Rgad := r_RGAD
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miim.io.RStat := r_RStat
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miim.io.ScanStat := r_ScanStat
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miim.io.mdi := io.mii.mdi
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Busy_stat := miim.io.Busy
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LinkFail := miim.io.LinkFail
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NValid_stat := miim.io.Nvalid
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Prsd := miim.io.Prsd
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WCtrlDataStart := miim.io.WCtrlDataStart
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RStatStart := miim.io.RStatStart
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UpdateMIIRX_DATAReg := miim.io.UpdateMIIRX_DATAReg
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io.mii.mdc := miim.io.mdc
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io.mii.mdo := miim.io.mdo
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io.mii.mdoEn := miim.io.mdoEn
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val r_RecSmall = Wire(Bool())
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val r_LoopBck = Wire(Bool())
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val r_TxEn = Wire(Bool())
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val r_RxEn = Wire(Bool())
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val MRxDV_Lb = Wire(Bool())
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val MRxErr_Lb = Wire(Bool())
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val MRxD_Lb = Wire(UInt(4.W))
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val Transmitting = Wire(Bool())
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val r_HugEn = Wire(Bool())
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val r_DlyCrcEn = Wire(Bool())
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val r_MaxFL = Wire(UInt(16.W))
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val r_MinFL = Wire(UInt(16.W))
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val ShortFrame = Wire(Bool())
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val DribbleNibble = Wire(Bool())
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val ReceivedPacketTooBig = Wire(Bool())
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val r_MAC = Wire(UInt(48.W))
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val LoadRxStatus = Wire(Bool())
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val r_HASH0 = Wire(UInt(32.W))
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val r_HASH1 = Wire(UInt(32.W))
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val r_TxBDNum = Wire(UInt(8.W))
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val r_IPGT = Wire(UInt(7.W))
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val r_IPGR1 = Wire(UInt(7.W))
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val r_IPGR2 = Wire(UInt(7.W))
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val r_CollValid = Wire(UInt(6.W))
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val r_TxPauseTV = Wire(UInt(16.W))
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val r_TxPauseRq = Wire(Bool())
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val r_MaxRet = Wire(UInt(4.W))
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val r_NoBckof = Wire(Bool())
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val r_ExDfrEn = Wire(Bool())
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val r_TxFlow = Wire(Bool())
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val r_IFG = Wire(Bool())
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val TxB_IRQ = Wire(Bool())
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val TxE_IRQ = Wire(Bool())
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val RxB_IRQ = Wire(Bool())
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val RxE_IRQ = Wire(Bool())
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val Busy_IRQ = Wire(Bool())
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val r_Pad = Wire(Bool())
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val r_CrcEn = Wire(Bool())
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val r_FullD = Wire(Bool())
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val r_Pro = Wire(Bool())
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val r_Bro = Wire(Bool())
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val r_NoPre = Wire(Bool())
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val r_RxFlow = Wire(Bool())
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val r_PassAll = Wire(Bool())
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val TxCtrlEndFrm = Wire(Bool())
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val StartTxDone = Wire(Bool())
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val SetPauseTimer = Wire(Bool())
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val TxUsedDataIn = Wire(Bool())
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val TxDoneIn = Wire(Bool())
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val TxAbortIn = Wire(Bool())
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val PerPacketPad = Wire(Bool())
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val PadOut = Wire(Bool())
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val PerPacketCrcEn = Wire(Bool())
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val CrcEnOut = Wire(Bool())
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val TxStartFrmOut = Wire(Bool())
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val TxEndFrmOut = Wire(Bool())
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val ReceivedPauseFrm = Wire(Bool())
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val ControlFrmAddressOK = Wire(Bool())
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val RxStatusWriteLatchedSync = Wire(Bool())
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val LateCollision = Wire(Bool())
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val DeferIndication = Wire(Bool())
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val LateCollLatched = Wire(Bool())
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val DeferLatched = Wire(Bool())
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val RstDeferLatched = Wire(Bool())
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val CarrierSenseLost = Wire(Bool())
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dontTouch(r_RecSmall )
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dontTouch(r_LoopBck )
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dontTouch(r_TxEn )
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dontTouch(r_RxEn )
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dontTouch(MRxDV_Lb )
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dontTouch(MRxErr_Lb )
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dontTouch(MRxD_Lb )
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dontTouch(Transmitting )
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dontTouch(r_HugEn )
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dontTouch(r_DlyCrcEn )
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dontTouch(r_MaxFL )
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dontTouch(r_MinFL )
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dontTouch(ShortFrame )
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dontTouch(DribbleNibble )
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dontTouch(ReceivedPacketTooBig )
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dontTouch(r_MAC )
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dontTouch(LoadRxStatus )
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dontTouch(r_HASH0 )
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dontTouch(r_HASH1 )
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dontTouch(r_TxBDNum )
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dontTouch(r_IPGT )
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dontTouch(r_IPGR1 )
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dontTouch(r_IPGR2 )
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dontTouch(r_CollValid )
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dontTouch(r_TxPauseTV )
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dontTouch(r_TxPauseRq )
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dontTouch(r_MaxRet )
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dontTouch(r_NoBckof )
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dontTouch(r_ExDfrEn )
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dontTouch(r_TxFlow )
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dontTouch(r_IFG )
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dontTouch(TxB_IRQ )
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dontTouch(TxE_IRQ )
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dontTouch(RxB_IRQ )
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dontTouch(RxE_IRQ )
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dontTouch(Busy_IRQ )
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dontTouch(r_Pad )
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dontTouch(r_CrcEn )
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dontTouch(r_FullD )
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dontTouch(r_Pro )
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dontTouch(r_Bro )
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dontTouch(r_NoPre )
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dontTouch(r_RxFlow )
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dontTouch(r_PassAll )
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dontTouch(TxCtrlEndFrm )
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dontTouch(StartTxDone )
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dontTouch(SetPauseTimer )
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dontTouch(TxUsedDataIn )
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dontTouch(TxDoneIn )
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dontTouch(TxAbortIn )
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dontTouch(PerPacketPad )
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dontTouch(PadOut )
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dontTouch(PerPacketCrcEn )
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dontTouch(CrcEnOut )
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dontTouch(TxStartFrmOut )
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dontTouch(TxEndFrmOut )
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dontTouch(ReceivedPauseFrm )
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dontTouch(ControlFrmAddressOK )
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dontTouch(RxStatusWriteLatchedSync )
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dontTouch(LateCollision )
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dontTouch(DeferIndication )
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dontTouch(LateCollLatched )
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dontTouch(DeferLatched )
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dontTouch(RstDeferLatched )
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dontTouch(CarrierSenseLost )
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// val ethReg = Module(new MacReg(outer.configNode))
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io.cfg.WCtrlDataStart := WCtrlDataStart
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io.cfg.RStatStart := RStatStart
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io.cfg.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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io.cfg.Prsd := Prsd
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io.cfg.NValid_stat := NValid_stat
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io.cfg.Busy_stat := Busy_stat
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io.cfg.LinkFail := LinkFail
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io.cfg.TxB_IRQ := TxB_IRQ
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io.cfg.TxE_IRQ := TxE_IRQ
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io.cfg.RxB_IRQ := RxB_IRQ
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io.cfg.RxE_IRQ := RxE_IRQ
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io.cfg.Busy_IRQ := Busy_IRQ
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io.cfg.RstTxPauseRq := RstTxPauseRq
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io.cfg.TxCtrlEndFrm := TxCtrlEndFrm
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io.cfg.StartTxDone := StartTxDone
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io.cfg.TxClk := io.mii.mtx_clk_pad_i
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io.cfg.RxClk := io.mii.mrx_clk_pad_i
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io.cfg.SetPauseTimer := SetPauseTimer
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r_RecSmall := io.cfg.r_RecSmall
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r_Pad := io.cfg.r_Pad
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r_HugEn := io.cfg.r_HugEn
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r_CrcEn := io.cfg.r_CrcEn
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r_DlyCrcEn := io.cfg.r_DlyCrcEn
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r_FullD := io.cfg.r_FullD
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r_ExDfrEn := io.cfg.r_ExDfrEn
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r_NoBckof := io.cfg.r_NoBckof
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r_LoopBck := io.cfg.r_LoopBck
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r_IFG := io.cfg.r_IFG
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r_Pro := io.cfg.r_Pro
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r_Bro := io.cfg.r_Bro
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r_NoPre := io.cfg.r_NoPre
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r_TxEn := io.cfg.r_TxEn
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r_RxEn := io.cfg.r_RxEn
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r_HASH0 := io.cfg.r_HASH0
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r_HASH1 := io.cfg.r_HASH1
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r_IPGT := io.cfg.r_IPGT
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r_IPGR1 := io.cfg.r_IPGR1
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r_IPGR2 := io.cfg.r_IPGR2
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r_MinFL := io.cfg.r_MinFL
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r_MaxFL := io.cfg.r_MaxFL
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r_MaxRet := io.cfg.r_MaxRet
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r_CollValid := io.cfg.r_CollValid
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r_TxFlow := io.cfg.r_TxFlow
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r_RxFlow := io.cfg.r_RxFlow
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r_PassAll := io.cfg.r_PassAll
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r_MiiNoPre := io.cfg.r_MiiNoPre
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r_ClkDiv := io.cfg.r_ClkDiv
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r_WCtrlData := io.cfg.r_WCtrlData
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r_RStat := io.cfg.r_RStat
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r_ScanStat := io.cfg.r_ScanStat
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r_RGAD := io.cfg.r_RGAD
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r_FIAD := io.cfg.r_FIAD
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r_CtrlData := io.cfg.r_CtrlData
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r_MAC := io.cfg.r_MAC
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r_TxBDNum := io.cfg.r_TxBDNum
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r_TxPauseTV := io.cfg.r_TxPauseTV
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r_TxPauseRq := io.cfg.r_TxPauseRq
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val RxData = Wire(UInt(8.W))
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val RxValid = Wire(Bool())
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val RxStartFrm = Wire(Bool())
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val RxEndFrm = Wire(Bool())
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val RxAbort = Wire(Bool())
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val WillTransmit = Wire(Bool())
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val ResetCollision = Wire(Bool())
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val TxDataOut = Wire(UInt(8.W))
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val WillSendControlFrame = Wire(Bool())
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val ReceiveEnd = Wire(Bool())
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val ReceivedPacketGood = Wire(Bool())
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val ReceivedLengthOK = Wire(Bool())
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val InvalidSymbol = Wire(Bool())
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val LatchedCrcError = Wire(Bool())
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val RxLateCollision = Wire(Bool())
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val RetryCntLatched = Wire(UInt(4.W))
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val RetryCnt = Wire(UInt(4.W))
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val StartTxAbort = Wire(Bool())
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val MaxCollisionOccured = Wire(Bool())
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val RetryLimit = Wire(Bool())
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val StatePreamble = Wire(Bool())
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val StateData = Wire(UInt(2.W))
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dontTouch(RxData )
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dontTouch(RxValid )
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dontTouch(RxStartFrm )
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dontTouch(RxEndFrm )
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dontTouch(RxAbort )
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dontTouch(WillTransmit )
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dontTouch(ResetCollision )
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dontTouch(TxDataOut )
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dontTouch(WillSendControlFrame)
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dontTouch(ReceiveEnd )
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dontTouch(ReceivedPacketGood )
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dontTouch(ReceivedLengthOK )
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dontTouch(InvalidSymbol )
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dontTouch(LatchedCrcError )
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dontTouch(RxLateCollision )
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dontTouch(RetryCntLatched )
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dontTouch(RetryCnt )
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dontTouch(StartTxAbort )
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dontTouch(MaxCollisionOccured )
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dontTouch(RetryLimit )
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dontTouch(StatePreamble )
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dontTouch(StateData )
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// Connecting MACControl
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val maccontrol = Module(new MacControl)
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maccontrol.io.MTxClk := io.mii.mtx_clk_pad_i
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maccontrol.io.MRxClk := io.mii.mrx_clk_pad_i
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maccontrol.io.asyncReset := io.asyncReset
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maccontrol.io.TPauseRq := TPauseRq
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maccontrol.io.TxDataIn := TxData
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maccontrol.io.TxStartFrmIn := TxStartFrm
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maccontrol.io.TxUsedDataIn := TxUsedDataIn
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maccontrol.io.TxEndFrmIn := TxEndFrm
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maccontrol.io.TxDoneIn := TxDoneIn
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maccontrol.io.TxAbortIn := TxAbortIn
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maccontrol.io.PadIn := r_Pad | PerPacketPad
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maccontrol.io.CrcEnIn := r_CrcEn | PerPacketCrcEn
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maccontrol.io.RxData := RxData
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maccontrol.io.RxValid := RxValid
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maccontrol.io.RxStartFrm := RxStartFrm
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maccontrol.io.RxEndFrm := RxEndFrm
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maccontrol.io.ReceiveEnd := ReceiveEnd
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maccontrol.io.ReceivedPacketGood := ReceivedPacketGood
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maccontrol.io.ReceivedLengthOK := ReceivedLengthOK
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maccontrol.io.TxFlow := r_TxFlow
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maccontrol.io.RxFlow := r_RxFlow
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maccontrol.io.DlyCrcEn := r_DlyCrcEn
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maccontrol.io.TxPauseTV := r_TxPauseTV
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maccontrol.io.MAC := r_MAC
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maccontrol.io.RxStatusWriteLatched_sync2 := RxStatusWriteLatchedSync
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maccontrol.io.r_PassAll := r_PassAll
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TxDataOut := maccontrol.io.TxDataOut
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TxStartFrmOut := maccontrol.io.TxStartFrmOut
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TxEndFrmOut := maccontrol.io.TxEndFrmOut
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TxDone := maccontrol.io.TxDoneOut
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TxAbort := maccontrol.io.TxAbortOut
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TxUsedData := maccontrol.io.TxUsedDataOut
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PadOut := maccontrol.io.PadOut
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CrcEnOut := maccontrol.io.CrcEnOut
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WillSendControlFrame := maccontrol.io.WillSendControlFrame
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TxCtrlEndFrm := maccontrol.io.TxCtrlEndFrm
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ReceivedPauseFrm := maccontrol.io.ReceivedPauseFrm
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ControlFrmAddressOK := maccontrol.io.ControlFrmAddressOK
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SetPauseTimer := maccontrol.io.SetPauseTimer
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val TxCarrierSense = Wire(Bool())
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val Collision = Wire(Bool())
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val CarrierSense_Tx2 = Wire(Bool())
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val RxEnSync = Wire(Bool())
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dontTouch(TxCarrierSense )
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dontTouch(Collision )
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dontTouch(CarrierSense_Tx2)
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dontTouch(RxEnSync )
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io.isLoopBack := r_LoopBck
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// Muxed MII receive data valid
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MRxDV_Lb := Mux(r_LoopBck, io.mii.mtxen_pad_o, io.mii.mrxdv_pad_i & RxEnSync)
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// Muxed MII Receive Error
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MRxErr_Lb := Mux(r_LoopBck, io.mii.mtxerr_pad_o, io.mii.mrxerr_pad_i & RxEnSync)
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// Muxed MII Receive Data
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MRxD_Lb := Mux(r_LoopBck, io.mii.mtxd_pad_o, io.mii.mrxd_pad_i)
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val txethmac = withClockAndReset(io.mii.mtx_clk_pad_i.asClock, io.asyncReset)( Module(new MacTx))
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txethmac.io.TxStartFrm := TxStartFrmOut
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txethmac.io.TxEndFrm := TxEndFrmOut
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txethmac.io.TxData := TxDataOut
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txethmac.io.CarrierSense := TxCarrierSense
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txethmac.io.Collision := Collision
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txethmac.io.Pad := PadOut
|
|
txethmac.io.CrcEn := CrcEnOut
|
|
txethmac.io.FullD := r_FullD
|
|
txethmac.io.HugEn := r_HugEn
|
|
txethmac.io.DlyCrcEn := r_DlyCrcEn
|
|
txethmac.io.MinFL := r_MinFL
|
|
txethmac.io.MaxFL := r_MaxFL
|
|
txethmac.io.IPGT := r_IPGT
|
|
txethmac.io.IPGR1 := r_IPGR1
|
|
txethmac.io.IPGR2 := r_IPGR2
|
|
txethmac.io.CollValid := r_CollValid
|
|
txethmac.io.MaxRet := r_MaxRet
|
|
txethmac.io.NoBckof := r_NoBckof
|
|
txethmac.io.ExDfrEn := r_ExDfrEn
|
|
|
|
io.mii.mtxd_pad_o := txethmac.io.MTxD
|
|
io.mii.mtxen_pad_o := txethmac.io.MTxEn
|
|
io.mii.mtxerr_pad_o := txethmac.io.MTxErr
|
|
TxDoneIn := txethmac.io.TxDone
|
|
TxRetry := txethmac.io.TxRetry
|
|
TxAbortIn := txethmac.io.TxAbort
|
|
TxUsedDataIn := txethmac.io.TxUsedData
|
|
WillTransmit := txethmac.io.WillTransmit
|
|
ResetCollision := txethmac.io.ResetCollision
|
|
RetryCnt := txethmac.io.RetryCnt
|
|
StartTxDone := txethmac.io.StartTxDone
|
|
StartTxAbort := txethmac.io.StartTxAbort
|
|
MaxCollisionOccured := txethmac.io.MaxCollisionOccured
|
|
LateCollision := txethmac.io.LateCollision
|
|
DeferIndication := txethmac.io.DeferIndication
|
|
StatePreamble := txethmac.io.StatePreamble
|
|
StateData := txethmac.io.StateData
|
|
|
|
|
|
|
|
|
|
|
|
val RxByteCnt = Wire(UInt(16.W))
|
|
val RxByteCntEq0 = Wire(Bool())
|
|
val RxByteCntGreat2 = Wire(Bool())
|
|
val RxByteCntMaxFrame = Wire(Bool())
|
|
val RxCrcError = Wire(Bool())
|
|
val RxStateIdle = Wire(Bool())
|
|
val RxStatePreamble = Wire(Bool())
|
|
val RxStateSFD = Wire(Bool())
|
|
val RxStateData = Wire(UInt(2.W))
|
|
val AddressMiss = Wire(Bool())
|
|
|
|
|
|
dontTouch(RxByteCnt )
|
|
dontTouch(RxByteCntEq0 )
|
|
dontTouch(RxByteCntGreat2 )
|
|
dontTouch(RxByteCntMaxFrame)
|
|
dontTouch(RxCrcError )
|
|
dontTouch(RxStateIdle )
|
|
dontTouch(RxStatePreamble )
|
|
dontTouch(RxStateSFD )
|
|
dontTouch(RxStateData )
|
|
dontTouch(AddressMiss )
|
|
|
|
val rxethmac = withClockAndReset(io.mii.mrx_clk_pad_i.asClock, io.asyncReset)( Module(new MacRx))
|
|
|
|
rxethmac.io.MRxDV := MRxDV_Lb
|
|
rxethmac.io.MRxD := MRxD_Lb
|
|
rxethmac.io.Transmitting := Transmitting
|
|
rxethmac.io.HugEn := r_HugEn
|
|
rxethmac.io.DlyCrcEn := r_DlyCrcEn
|
|
rxethmac.io.MaxFL := r_MaxFL
|
|
rxethmac.io.r_IFG := r_IFG
|
|
rxethmac.io.MAC := r_MAC
|
|
rxethmac.io.r_Bro := r_Bro
|
|
rxethmac.io.r_Pro := r_Pro
|
|
rxethmac.io.r_HASH0 := r_HASH0
|
|
rxethmac.io.r_HASH1 := r_HASH1
|
|
rxethmac.io.PassAll := r_PassAll
|
|
rxethmac.io.ControlFrmAddressOK := ControlFrmAddressOK
|
|
|
|
RxData := rxethmac.io.RxData
|
|
RxValid := rxethmac.io.RxValid
|
|
RxStartFrm := rxethmac.io.RxStartFrm
|
|
RxEndFrm := rxethmac.io.RxEndFrm
|
|
RxByteCnt := rxethmac.io.ByteCnt
|
|
RxByteCntEq0 := rxethmac.io.ByteCntEq0
|
|
RxByteCntGreat2 := rxethmac.io.ByteCntGreat2
|
|
RxByteCntMaxFrame := rxethmac.io.ByteCntMaxFrame
|
|
RxCrcError := rxethmac.io.CrcError
|
|
RxStateIdle := rxethmac.io.StateIdle
|
|
RxStatePreamble := rxethmac.io.StatePreamble
|
|
RxStateSFD := rxethmac.io.StateSFD
|
|
RxStateData := rxethmac.io.StateData
|
|
RxAbort := rxethmac.io.RxAbort
|
|
AddressMiss := rxethmac.io.AddressMiss
|
|
|
|
|
|
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
|
// MII Carrier Sense Synchronization
|
|
CarrierSense_Tx2 := ShiftRegister(io.mii.mcrs_pad_i, 2, false.B, true.B)
|
|
|
|
TxCarrierSense := ~r_FullD & CarrierSense_Tx2
|
|
|
|
val Collision_Tx1 = RegNext(io.mii.mcoll_pad_i, false.B)
|
|
val Collision_Tx2 = RegInit(false.B)
|
|
|
|
when(ResetCollision){
|
|
Collision_Tx2 := false.B
|
|
} .elsewhen(Collision_Tx1){
|
|
Collision_Tx2 := true.B
|
|
}
|
|
|
|
|
|
// Synchronized Collision
|
|
Collision := ~r_FullD & Collision_Tx2
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
|
val WillTransmit_q = ShiftRegister(WillTransmit, 2, false.B, true.B)
|
|
|
|
Transmitting := ~r_FullD & WillTransmit_q
|
|
RxEnSync := RegEnable( ShiftRegister(r_RxEn, 2), false.B, ~io.mii.mrxdv_pad_i)
|
|
}
|
|
|
|
|
|
|
|
|
|
// Synchronizing WillSendControlFrame to WB_CLK;
|
|
val WillSendControlFrame_sync = ShiftRegisters(WillSendControlFrame, 3, false.B, true.B)
|
|
|
|
when(true.B){
|
|
RstTxPauseRq := WillSendControlFrame_sync(1) & ~WillSendControlFrame_sync(2)
|
|
}
|
|
|
|
|
|
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
|
val TxPauseRq_sync = ShiftRegisters((r_TxPauseRq & r_TxFlow), 3, false.B, true.B )
|
|
|
|
TPauseRq := RegNext( TxPauseRq_sync(1) & (~TxPauseRq_sync(2)), false.B )
|
|
}
|
|
|
|
val LatchedMRxErr = Wire(Bool())
|
|
|
|
|
|
|
|
|
|
val RxAbort_latch_wire = Wire(Bool())
|
|
val RxAbort_wb = ShiftRegister( RxAbort_latch_wire, 2, false.B, true.B )
|
|
|
|
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, reset.asAsyncReset ) {
|
|
val RxAbort_latch = RegInit(false.B); RxAbort_latch_wire := RxAbort_latch
|
|
val RxAbortRst = ShiftRegister( RxAbort_wb, 2, false.B, true.B )
|
|
|
|
// Synchronizing RxAbort to the WISHBONE clock
|
|
when(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))){
|
|
RxAbort_latch := true.B
|
|
} .elsewhen(RxAbortRst){
|
|
RxAbort_latch := false.B
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val wishbone = Module(new MacTileLink)
|
|
|
|
|
|
wishbone.io.RetryCntLatched := RetryCntLatched
|
|
wishbone.io.RetryLimit := RetryLimit
|
|
wishbone.io.LateCollLatched := LateCollLatched
|
|
wishbone.io.DeferLatched := DeferLatched
|
|
wishbone.io.CarrierSenseLost := CarrierSenseLost
|
|
|
|
PerPacketCrcEn := wishbone.io.PerPacketCrcEn
|
|
PerPacketPad := wishbone.io.PerPacketPad
|
|
|
|
wishbone.io.r_TxEn := r_TxEn
|
|
wishbone.io.r_RxEn := r_RxEn
|
|
TxB_IRQ := false.B
|
|
TxE_IRQ := false.B
|
|
RxB_IRQ := false.B
|
|
RxE_IRQ := false.B
|
|
|
|
|
|
|
|
|
|
val macstatus = Module(new MacStatus)
|
|
|
|
macstatus.io.asyncReset := io.asyncReset
|
|
macstatus.io.MRxClk := io.mii.mrx_clk_pad_i
|
|
macstatus.io.RxCrcError := RxCrcError
|
|
macstatus.io.MRxErr := MRxErr_Lb
|
|
macstatus.io.MRxDV := MRxDV_Lb
|
|
macstatus.io.RxStateSFD := RxStateSFD
|
|
macstatus.io.RxStateData := RxStateData
|
|
macstatus.io.RxStatePreamble := RxStatePreamble
|
|
macstatus.io.RxStateIdle := RxStateIdle
|
|
macstatus.io.Transmitting := Transmitting
|
|
macstatus.io.RxByteCnt := RxByteCnt
|
|
macstatus.io.RxByteCntEq0 := RxByteCntEq0
|
|
macstatus.io.RxByteCntGreat2 := RxByteCntGreat2
|
|
macstatus.io.RxByteCntMaxFrame := RxByteCntMaxFrame
|
|
macstatus.io.MRxD := MRxD_Lb
|
|
macstatus.io.Collision := io.mii.mcoll_pad_i
|
|
macstatus.io.CollValid := r_CollValid
|
|
macstatus.io.r_RecSmall := r_RecSmall
|
|
macstatus.io.r_MinFL := r_MinFL
|
|
macstatus.io.r_MaxFL := r_MaxFL
|
|
macstatus.io.r_HugEn := r_HugEn
|
|
macstatus.io.StartTxDone := StartTxDone
|
|
macstatus.io.StartTxAbort := StartTxAbort
|
|
macstatus.io.RetryCnt := RetryCnt
|
|
macstatus.io.MTxClk := io.mii.mtx_clk_pad_i
|
|
macstatus.io.MaxCollisionOccured := MaxCollisionOccured
|
|
macstatus.io.LateCollision := LateCollision
|
|
macstatus.io.DeferIndication := DeferIndication
|
|
macstatus.io.TxStartFrm := TxStartFrmOut
|
|
macstatus.io.StatePreamble := StatePreamble
|
|
macstatus.io.StateData := StateData
|
|
macstatus.io.CarrierSense := CarrierSense_Tx2
|
|
macstatus.io.TxUsedData := TxUsedDataIn
|
|
macstatus.io.Loopback := r_LoopBck
|
|
macstatus.io.r_FullD := r_FullD
|
|
macstatus.io.RstDeferLatched := RstDeferLatched
|
|
|
|
ReceivedLengthOK := macstatus.io.ReceivedLengthOK
|
|
ReceiveEnd := macstatus.io.ReceiveEnd
|
|
ReceivedPacketGood := macstatus.io.ReceivedPacketGood
|
|
InvalidSymbol := macstatus.io.InvalidSymbol
|
|
LatchedCrcError := macstatus.io.LatchedCrcError
|
|
RxLateCollision := macstatus.io.RxLateCollision
|
|
ShortFrame := macstatus.io.ShortFrame
|
|
DribbleNibble := macstatus.io.DribbleNibble
|
|
ReceivedPacketTooBig := macstatus.io.ReceivedPacketTooBig
|
|
LoadRxStatus := macstatus.io.LoadRxStatus
|
|
RetryCntLatched := macstatus.io.RetryCntLatched
|
|
RetryLimit := macstatus.io.RetryLimit
|
|
LateCollLatched := macstatus.io.LateCollLatched
|
|
DeferLatched := macstatus.io.DeferLatched
|
|
CarrierSenseLost := macstatus.io.CarrierSenseLost
|
|
LatchedMRxErr := macstatus.io.LatchedMRxErr
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val macTileLinkTx = withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ) (Module(new MacTileLinkTx))
|
|
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
val ReadTxDataFromFifo_sync = ShiftRegister( macTileLinkTx.io.ReadTxDataFromFifo_tck, 2, false.B, true.B)
|
|
wishbone.io.ReadTxDataFromFifo_sync := ReadTxDataFromFifo_sync
|
|
|
|
withClockAndReset( io.mii.mtx_clk_pad_i.asClock, io.asyncReset ){
|
|
macTileLinkTx.io.BlockingTxStatusWrite_sync := ShiftRegister( wishbone.io.BlockingTxStatusWrite, 2, false.B, true.B)
|
|
macTileLinkTx.io.TxStartFrm_sync := ShiftRegister( wishbone.io.TxStartFrm_wb, 2, false.B, true.B ) // Synchronizing TxStartFrm_wb to MTxClk
|
|
macTileLinkTx.io.ReadTxDataFromFifo_syncb := ShiftRegister( ReadTxDataFromFifo_sync, 2, false.B, true.B)
|
|
}
|
|
|
|
|
|
wishbone.io.TxStartFrm_syncb := ShiftRegister( macTileLinkTx.io.TxStartFrm_sync, 2, false.B, true.B )
|
|
|
|
RstDeferLatched := macTileLinkTx.io.RstDeferLatched
|
|
TxStartFrm := macTileLinkTx.io.TxStartFrm
|
|
TxEndFrm := macTileLinkTx.io.TxEndFrm
|
|
TxData := macTileLinkTx.io.TxData
|
|
|
|
|
|
macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
|
|
macTileLinkTx.io.TxValidBytesLatched := wishbone.io.TxValidBytesLatched
|
|
macTileLinkTx.io.TxEndFrm_wb := wishbone.io.TxEndFrm_wb
|
|
|
|
wishbone.io.TxUsedData := TxUsedData
|
|
macTileLinkTx.io.TxUsedData := TxUsedData
|
|
|
|
macTileLinkTx.io.TxRetry := TxRetry
|
|
macTileLinkTx.io.TxAbort := TxAbort
|
|
macTileLinkTx.io.TxDone := TxDone
|
|
|
|
wishbone.io.TxRetrySync := ShiftRegister( TxRetry, 2, false.B, true.B )
|
|
wishbone.io.TxAbortSync := ShiftRegister( TxAbort, 2, false.B, true.B )
|
|
wishbone.io.TxDoneSync := ShiftRegister( TxDone, 2, false.B, true.B )
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val macTileLinkRx = withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) ( Module(new MacTileLinkRx) )
|
|
|
|
|
|
|
|
wishbone.io.RxDataLatched2_rxclk := macTileLinkRx.io.RxDataLatched2
|
|
|
|
val WriteRxDataToFifoSync = ShiftRegister(macTileLinkRx.io.WriteRxDataToFifo, 2, false.B, true.B)
|
|
wishbone.io.WriteRxDataToFifoSync := WriteRxDataToFifoSync
|
|
|
|
val RxAbortSync = ShiftRegister( macTileLinkRx.io.RxAbortLatched, 2, false.B, true.B )
|
|
wishbone.io.RxAbortSync := RxAbortSync
|
|
|
|
val ShiftEndedSync = ShiftRegister( macTileLinkRx.io.ShiftEnded_rck, 2, false.B, true.B )
|
|
wishbone.io.ShiftEndedSync := ShiftEndedSync
|
|
|
|
|
|
|
|
|
|
|
|
wishbone.io.LatchedRxLength_rxclk := macTileLinkRx.io.LatchedRxLength
|
|
wishbone.io.RxStatusInLatched_rxclk := macTileLinkRx.io.RxStatusInLatched
|
|
|
|
|
|
|
|
// Busy Interrupt
|
|
val Busy_IRQ_sync = ShiftRegister(macTileLinkRx.io.Busy_IRQ_rck, 2, false.B, true.B)
|
|
Busy_IRQ := Busy_IRQ_sync & ~RegNext(Busy_IRQ_sync, false.B)
|
|
|
|
withClockAndReset( io.mii.mrx_clk_pad_i.asClock, io.asyncReset ) {
|
|
val ShiftEndedSyncb = ShiftRegister( ShiftEndedSync, 2, false.B, true.B)
|
|
RxStatusWriteLatchedSync := ShiftEndedSyncb
|
|
macTileLinkRx.io.ShiftEndedSyncb := ShiftEndedSyncb
|
|
macTileLinkRx.io.RxAbortSyncb := ShiftRegister( RxAbortSync, 2, false.B, true.B )
|
|
macTileLinkRx.io.Busy_IRQ_syncb := ShiftRegister( Busy_IRQ_sync, 2, false.B, true.B )
|
|
|
|
macTileLinkRx.io.WriteRxDataToFifoSyncb := ShiftRegister( WriteRxDataToFifoSync, 2, false.B, true.B )
|
|
macTileLinkRx.io.RxReady := ShiftRegister( wishbone.io.RxReady, 2, false.B, true.B )
|
|
}
|
|
|
|
macTileLinkRx.io.RxData := RxData
|
|
macTileLinkRx.io.RxAbort := RxAbort_latch_wire
|
|
macTileLinkRx.io.RxValid := RxValid
|
|
|
|
macTileLinkRx.io.RxStartFrm := RxStartFrm
|
|
macTileLinkRx.io.RxEndFrm := RxEndFrm
|
|
|
|
|
|
macTileLinkRx.io.RxLength := RxByteCnt
|
|
macTileLinkRx.io.LoadRxStatus := LoadRxStatus
|
|
macTileLinkRx.io.RxStatusIn := Cat(ReceivedPauseFrm, AddressMiss, false.B, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision)
|
|
|
|
|
|
wishbone.io.rxEnq <> io.rxEnq
|
|
wishbone.io.txDeq <> io.txDeq
|
|
}
|
|
|
|
|
|
|
|
|
|
|