From 0215add0d4bffbecb93e0ab22f2696cc8d290366 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 20 Oct 2023 14:42:15 +0800 Subject: [PATCH] =?UTF-8?q?rx=20DMA=E7=BC=96=E8=AF=91=E5=AE=8C=E6=88=90?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/Switch/MacRegisters.scala | 4 +- src/main/scala/Switch/RxBuff.scala | 26 ++++----- src/main/scala/Switch/Switch.scala | 11 +++- src/main/scala/Switch/SwitchMux.scala | 63 +++++++++++---------- src/main/scala/Switch/TxBuff.scala | 7 ++- src/main/scala/Switch/WithSwitch.scala | 2 +- src/main/scala/Switch/mac/MAC.scala | 2 +- src/main/scala/Switch/mac/MacTilelink.scala | 4 +- 8 files changed, 63 insertions(+), 56 deletions(-) diff --git a/src/main/scala/Switch/MacRegisters.scala b/src/main/scala/Switch/MacRegisters.scala index 6a704cc..b5924cb 100644 --- a/src/main/scala/Switch/MacRegisters.scala +++ b/src/main/scala/Switch/MacRegisters.scala @@ -324,8 +324,8 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out )), ( 30 << 2 ) -> - RegFieldGroup("BD", Some("bd"), - RegField.w(1, RegWriteFn((valid, data) => { io.triTx := (valid & (data === 1.U)) ; true.B} ),Some(RegFieldDesc("bd", "bd", reset=Some(0x0)))) ++ Seq( + RegFieldGroup("BD", Some("bd"), Seq( + RegField.w(1, RegWriteFn((valid, data) => { io.triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", "bd", reset=Some(0x0))) )), ) diff --git a/src/main/scala/Switch/RxBuff.scala b/src/main/scala/Switch/RxBuff.scala index 854245a..2471f73 100644 --- a/src/main/scala/Switch/RxBuff.scala +++ b/src/main/scala/Switch/RxBuff.scala @@ -112,7 +112,7 @@ trait RxBuffEnq{ this: RxBuffBase => } -trait RxBuffDeq{ this: RxBuff => +trait RxBuffDeq{ this: RxBuffBase => when( io.deq.header.fire ){ when( isDeqPi ) { hValid(0) := false.B } @@ -123,11 +123,6 @@ trait RxBuffDeq{ this: RxBuff => } - Mux1H(Seq( isDeqPi -> hValid(0), isDeqPo -> hValid(1) )) - io.header.bits := Mux1H(Seq( isDeqPi -> hValid(0), isDeqPo -> hValid(1) )) - - - when( io.deq.ctrl.fire ){ isDeqPi := ~isDeqPi when( isDeqPi ) { cValid(0) := false.B } @@ -139,18 +134,21 @@ trait RxBuffDeq{ this: RxBuff => when( isDeqPi ){ - io.deq <> buff(0).io.deq + io.deq.data <> buff(0).io.deq + buff(1).io.deq.ready := false.B - io.header.valid := hValid(0) - io.header.bits := header(0) + io.deq.header.valid := hValid(0) + io.deq.header.bits := header(0) io.deq.ctrl.valid := cValid(0) & ~buff(0).io.deq.valid io.deq.ctrl.bits := info(0) - } .elsewhen( isDeqPo ){ - io.deq <> buff(1).io.deq + } .otherwise{ + assert( isDeqPo ) + io.deq.data <> buff(1).io.deq + buff(0).io.deq.ready := false.B - io.header.valid := hValid(1) - io.header.bits := header(1) + io.deq.header.valid := hValid(1) + io.deq.header.bits := header(1) io.deq.ctrl.valid := cValid(1) & ~buff(1).io.deq.valid io.deq.ctrl.bits := info(1) @@ -161,7 +159,7 @@ trait RxBuffDeq{ this: RxBuff => } -class RxBuff extends RxBuffRxBuff with RxBuffEnq with RxBuffDeq{ +class RxBuff extends RxBuffBase with RxBuffEnq with RxBuffDeq{ } diff --git a/src/main/scala/Switch/Switch.scala b/src/main/scala/Switch/Switch.scala index cc2076e..9f516ef 100644 --- a/src/main/scala/Switch/Switch.scala +++ b/src/main/scala/Switch/Switch.scala @@ -56,18 +56,23 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out outer.ethReg.module.io.asyncReset := io.asyncReset outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg - val switchMux = Module(new SwitchMux) + val switchMux = Module(new SwitchMux(dma_edge)) switchMux.io.rxEnq(0) <> mac(0).io.rxEnq switchMux.io.txDeq(0) <> mac(0).io.txDeq + switchMux.io.triTx := outer.ethReg.module.io.triTx - - + switchMux.io.dmaMst.D.bits := dma_bus.d.bits + switchMux.io.dmaMst.D.valid := dma_bus.d.valid + dma_bus.d.ready := switchMux.io.dmaMst.D.ready + dma_bus.a.valid := switchMux.io.dmaMst.A.valid + dma_bus.a.bits := switchMux.io.dmaMst.A.bits + switchMux.io.dmaMst.A.ready := dma_bus.a.ready diff --git a/src/main/scala/Switch/SwitchMux.scala b/src/main/scala/Switch/SwitchMux.scala index ad56632..4d0dbdb 100644 --- a/src/main/scala/Switch/SwitchMux.scala +++ b/src/main/scala/Switch/SwitchMux.scala @@ -4,7 +4,9 @@ import chisel3._ import chisel3.util._ - +import org.chipsalliance.cde.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ @@ -21,13 +23,19 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule val triTx = Input(Bool()) - val rxEnq = Vec(chn, new Receive_Enq_Bundle) - val txDeq = Vec(chn, Flipped(new Transmit_Deq_Bundle)) + val rxEnq = Vec(chn, Flipped(new Receive_Enq_Bundle)) + val txDeq = Vec(chn, new Transmit_Bundle) } val io: SwitchMuxIO = IO(new SwitchMuxIO) + val (_, _, isLastD, transDCnt) = edgeOut.count(io.dmaMst.D) + val rxBuff = Module(new RxBuff) + rxBuff.io.enq <> io.rxEnq(0) + + val txBuff = Module(new TxBuff) + txBuff.io.deq <> io.txDeq(0) def stateIdle = 0.U def stateRx = 1.U @@ -45,22 +53,15 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule def ptr = 0x8002000 - def txLength = 8 + def txLength = 8.U def PerPacketCrcEn = true.B def PerPacketPad = true.B - val rxBuff = Module(new RxBuff) - rxBuff.io.enq <> io.rxEnq(0) - - val txBuff = Module(new TxBuff) - txBuff.io.deq <> mac.io.txDeq(0) - - rxBuff.io.deq.ctrl.ready := stateCur === stateRx @@ -73,9 +74,9 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule } txBuff.io.enq.req.valid := txReqValid && stateCur === stateIdle - txBuff.io.enq.bits.txLength := txLength - txBuff.io.enq.bits.PerPacketCrcEn := PerPacketCrcEn - txBuff.io.enq.bits.PerPacketPad := PerPacketPad + txBuff.io.enq.req.bits.txLength := txLength + txBuff.io.enq.req.bits.PerPacketCrcEn := PerPacketCrcEn + txBuff.io.enq.req.bits.PerPacketPad := PerPacketPad @@ -94,34 +95,34 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule when( stateCur === stateIdle && stateNxt =/= stateIdle ){ dmaAddress := ptr.U - } .elsewhen( io.A.fire ){ + } .elsewhen( io.dmaMst.A.fire ){ dmaAddress := dmaAddress + 4.U } - rxBuff.io.deq.data.ready := io.A.ready & stateCur === stateRx - rxBuff.io.deq.header.ready := ~io.io.triTx && ~txReqValid + rxBuff.io.deq.data.ready := io.dmaMst.A.ready & stateCur === stateRx + rxBuff.io.deq.header.ready := ~io.triTx && ~txReqValid - when( io.A.fire ){ + when( io.dmaMst.A.fire & stateCur === stateTx ){ dmaTxAValid := false.B - } .elsewhen( txBuff.io.enq.req.fire ){ + } .elsewhen( txBuff.io.enq.req.fire | (io.dmaMst.D.fire & isLastD & stateCur === stateTx & dmaAddress >= (ptr.U + txLength)) ){ dmaTxAValid := true.B dmaTxABits := edgeOut.Get( fromSource = 0.U, toAddress = dmaAddress >> 2 << 2, - lgSize = log2Ceil(txLength).U, + lgSize = log2Ceil(32/8).U, )._2 } - io.A.valid := + io.dmaMst.A.valid := Mux1H(Seq( - stateCur === stateRx -> rxBuff.io.deq.data.valid, - stateCur === stateTx -> dmaTxAValid, + ( stateCur === stateRx ) -> rxBuff.io.deq.data.valid, + ( stateCur === stateTx ) -> dmaTxAValid, )) when( stateCur === stateRx ){ - io.A.bits := + io.dmaMst.A.bits := edgeOut.Put( fromSource = 0.U, toAddress = dmaAddress >> 2 << 2, @@ -130,20 +131,20 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule mask = "b1111".U, )._2 } .elsewhen( stateCur === stateTx ){ - io.A.bits := dmaTxABits + io.dmaMst.A.bits := dmaTxABits } .otherwise{ - io.A.bits := DontCare + io.dmaMst.A.bits := DontCare } - txBuff.io.enq.data.valid := io.D.valid & stateCur === stateTx - txBuff.io.enq.data.bits := io.D.bits.data + txBuff.io.enq.data.valid := io.dmaMst.D.valid & stateCur === stateTx + txBuff.io.enq.data.bits := io.dmaMst.D.bits.data - io.D.ready := + io.dmaMst.D.ready := Mux1H(Seq( - stateCur === stateRx -> true.B, - stateCur === stateTx -> txBuff.io.enq.data.ready, + ( stateCur === stateRx ) -> true.B, + ( stateCur === stateTx ) -> txBuff.io.enq.data.ready, )) diff --git a/src/main/scala/Switch/TxBuff.scala b/src/main/scala/Switch/TxBuff.scala index 1ebf4a2..387a2e7 100644 --- a/src/main/scala/Switch/TxBuff.scala +++ b/src/main/scala/Switch/TxBuff.scala @@ -39,13 +39,16 @@ class TxBuff extends Module{ val io: TxBuffIO = IO(new TxBuffIO) io.enq.data.ready := true.B - io.enq.ctrl.ready := true.B + io.enq.req.ready := true.B + + io.enq.resp.valid := false.B + io.enq.resp.bits := DontCare io.deq.data.valid := false.B io.deq.data.bits := 0.U io.deq.req.valid := false.B - io.deq.req.bits := 0.U.asTypeOf(new Transmit_Deq_Req_Bundle) + io.deq.req.bits := DontCare io.deq.resp.ready := true.B diff --git a/src/main/scala/Switch/WithSwitch.scala b/src/main/scala/Switch/WithSwitch.scala index 7075453..6cd0272 100644 --- a/src/main/scala/Switch/WithSwitch.scala +++ b/src/main/scala/Switch/WithSwitch.scala @@ -12,7 +12,7 @@ trait WithSwitchMix { this: BaseSubsystem => val switch = LazyModule(new Switch) - // sbus.coupleFrom("switch_mst") { _ := TLBuffer() := switch0.tlClientNode } + sbus.coupleFrom("switch_mst") { _ := TLBuffer() := switch.tlClientNode } // pbus.coupleTo("switch_cfg") { switch0.tlMasterNode := TLFragmenter(pbus) := _ } pbus.coupleTo("switch_cfg") { switch.ethReg.configNode := TLFragmenter(pbus) := _ } diff --git a/src/main/scala/Switch/mac/MAC.scala b/src/main/scala/Switch/mac/MAC.scala index 06d6574..3eebc96 100644 --- a/src/main/scala/Switch/mac/MAC.scala +++ b/src/main/scala/Switch/mac/MAC.scala @@ -31,7 +31,7 @@ class MacIO extends Bundle{ val mii = new MII val cfg = Flipped(new Mac_Config_Bundle) val rxEnq = new Receive_Enq_Bundle - val txDeq = Flipped(new Transmit_Deq_Bundle) + val txDeq = Flipped(new Transmit_Bundle) // val int_o = Output(Bool()) diff --git a/src/main/scala/Switch/mac/MacTilelink.scala b/src/main/scala/Switch/mac/MacTilelink.scala index 49aaf33..a2a1b5b 100644 --- a/src/main/scala/Switch/mac/MacTilelink.scala +++ b/src/main/scala/Switch/mac/MacTilelink.scala @@ -57,7 +57,7 @@ abstract class MacTileLinkBase() extends Module{ val rxEnq = new Receive_Enq_Bundle - val txDeq = Flipped(new Transmit_Deq_Bundle) + val txDeq = Flipped(new Transmit_Bundle) } @@ -164,7 +164,7 @@ abstract class MacTileLinkBase() extends Module{ val txRespValid = RegInit(false.B) - val txRespBits = Reg(new Transmit_Deq_Resp_Bundle) + val txRespBits = Reg(new Transmit_Resp_Bundle) io.txDeq.resp.valid := txRespValid io.txDeq.resp.bits := txRespBits