eb001/src/main/scala/backBoard/BackBoardMst.scala

package BACK

import chisel3._
import chisel3.util._




class FSMC_Port_Bundle extends Bundle{

  val ADIn  = Input(UInt(16.W))
  val ADOut = Output(UInt(16.W))
  val ADOEn = Output(Bool())
  val csn   = Input(Bool())
  val rdn   = Input(Bool())
  val wrn   = Input(Bool())
  val advn  = Input(Bool())
}

class LVDS_MST_Bundle extends Bundle{
  val frame_info_update_en = Output(Bool())
  val slave_type_num       = Output(UInt(8.W))
  val slave_data_length    = Output(UInt(8.W))
  val tx_start             = Output(Bool())

  val slave_link_num_valid = Input(Bool())
  val slave_link_num       = Input(UInt(7.W))

  val downstream_busy      = Input(Bool())
  val upstream_crc_valid   = Input(Bool())

  val closed_loop_err      = Input(Bool())
  val link_err_location    = Input(UInt(7.W))

  val upstream_cdr_err     = Input(Bool())
  val upstream_crc_err     = Input(Bool())

  val tx_data_ready        = Input(Bool())
  val tx_data_in           = Output(UInt(8.W))
  val rx_data_valid        = Input(Bool())
  val rx_data_out          = Input(UInt(8.W))
}



class BackBoardMstIO extends Bundle{
  val FSMC = new FSMC_Port_Bundle

  val oser_pclk = Input(Bool()) //10M
  val oser_fclk = Input(Bool()) //50M
  val ides_pclk = Input(Bool()) //100M
  val ides_fclk = Input(Bool()) //400M


  val interrupt = Output(Bool())

  val testIO = Input(Bool())

  val lvdsMst = new LVDS_MST_Bundle

}

class BackBoardMstBase extends Module{ //10M
  val io: BackBoardMstIO = IO(new BackBoardMstIO)

  val mirrorDown = Module(new MirrorSRAMDP())
  val mirrorUp   = Module(new MirrorSRAMDP())
  val mirrorReg  = Module(new MirrorSRAMDP())

  mirrorReg.io.addrB  := DontCare
  mirrorReg.io.datawB := DontCare
  mirrorReg.io.enwB   := false.B
  mirrorReg.io.enrB   := false.B

  assert( ~(mirrorReg.io.enwA & mirrorReg.io.enrA) )
  assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) )

  val ctrlTransmit = RegInit( false.B )
  val ctrlUnicast  = RegInit( false.B )
  val ctrlSynch    = RegInit( false.B )
  val ctrlInit     = RegInit( false.B )

  val slvNum  = RegInit(0.U(6.W))
  val interrupt = RegInit(false.B); io.interrupt := interrupt
  val slaveDataLength = Reg(UInt(8.W)) //(8/8)*32-1





  mirrorDown.io.clockA := io.ides_pclk.asBool //100M  
  mirrorDown.io.clockB := io.oser_pclk.asBool

  mirrorUp.io.clockA := io.ides_pclk.asBool   //100M
  mirrorUp.io.clockB := io.oser_pclk.asBool

  mirrorReg.io.clockA := io.ides_pclk.asBool //100M
  mirrorReg.io.clockB := io.oser_pclk.asBool //10M

  when(interrupt === true.B){
    interrupt := false.B
  }


}




trait BackBoardMstFSMC{ this: BackBoardMstBase =>

  withClockAndReset( io.ides_pclk.asClock, reset ){//100M

    io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn

    val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)

    val isAccessSRAM = ~latchAddr.extract(11) 
    val isAccessReg  =  latchAddr.extract(11)
    val isAccessDown = ~latchAddr.extract(10)
    val activeAddr   =  latchAddr(9,0)

    mirrorDown.io.addrA   := activeAddr
    mirrorDown.io.datawA  := io.FSMC.ADIn
    mirrorDown.io.enwA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & isAccessDown
    mirrorDown.io.enrA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & isAccessDown

    mirrorUp.io.addrA   := activeAddr
    mirrorUp.io.datawA  := io.FSMC.ADIn
    mirrorUp.io.enwA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & ~isAccessDown
    mirrorUp.io.enrA    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & ~isAccessDown

    mirrorReg.io.addrA  := activeAddr
    mirrorReg.io.datawA := io.FSMC.ADIn
    mirrorReg.io.enwA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
    mirrorReg.io.enrA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn

    io.FSMC.ADOut   := Mux( isAccessReg, mirrorReg.io.datarA, Mux( isAccessDown, mirrorDown.io.datarA, mirrorUp.io.datarA) )


  }

  //10M
  val testIOShift = ShiftRegisters(io.testIO, 3, false.B, true.B)
  when(~testIOShift(0) & io.testIO){

    mirrorReg.io.addrB  := 1.U
    mirrorReg.io.enrB   := true.B
  } .elsewhen( ~testIOShift(1) & testIOShift(0)){
    when( mirrorReg.io.datarB === 0.U ){
      ctrlInit   := true.B
    }

    when( mirrorReg.io.datarB === 1.U ){
      ctrlSynch   := true.B
    }

    when( mirrorReg.io.datarB === 5.U ){
      ctrlTransmit := true.B      
    }

    when( mirrorReg.io.datarB === 6.U ){
      ctrlUnicast := true.B      
    }
  }

}

abstract class BackBoardMstLVDSBase extends BackBoardMstBase 
with BackBoardMstFSMC
{


  val frame_info_update_en = RegInit(false.B)
  val slave_type_num       = RegInit(0.U(8.W))

  val tx_start             = RegInit(false.B)

  io.lvdsMst.frame_info_update_en := frame_info_update_en
  io.lvdsMst.slave_type_num       := slave_type_num
  io.lvdsMst.slave_data_length    := slaveDataLength
  io.lvdsMst.tx_start := tx_start

  val stateCur = RegInit(15.U(4.W))


}


trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>

  val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit
  val timeoutCnt = Reg(UInt(13.W))

  when(ctrlInit){
    when( isInitStart ){

      stateCur := 0.U
      frame_info_update_en := false.B
      slave_type_num       := 0.U
      tx_start := false.B
      
    } .elsewhen( stateCur === 0.U ){
      stateCur := 1.U

      // write statusInit
      mirrorReg.io.addrB  := 7.U
      mirrorReg.io.datawB := 0.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 1.U ){
      stateCur := 2.U

      //req slvnum
      mirrorReg.io.addrB := 2.U
      mirrorReg.io.enrB  := true.B

    } .elsewhen( stateCur === 2.U ){
      stateCur := 3.U

      //lock slvNum
      slvNum := mirrorReg.io.datarB

      //req slaveDataLength
      mirrorReg.io.addrB  := 6.U
      mirrorReg.io.enrB  := true.B

    }
    .elsewhen( stateCur === 3.U ){
      stateCur := 4.U

      //lock slaveDataLength
      slaveDataLength := mirrorReg.io.datarB

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b00".U(2.W), slvNum )
      // slaveDataLength      := slaveDataLength

      tx_start := false.B
    } .elsewhen( stateCur === 4.U ){ // tx start
      stateCur := 5.U
      timeoutCnt := 0.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 5.U ){
      tx_start := false.B
      timeoutCnt := timeoutCnt + 1.U

      when( io.lvdsMst.slave_link_num_valid ){
        stateCur := 6.U

        //linkNum 
        mirrorReg.io.addrB  := 5.U
        mirrorReg.io.datawB := io.lvdsMst.slave_link_num
        mirrorReg.io.enwB   := true.B

      }

      when( timeoutCnt === 6000.U ){
        stateCur := 6.U

        //linkNum 
        mirrorReg.io.addrB  := 5.U
        mirrorReg.io.datawB := 0.U
        mirrorReg.io.enwB   := true.B

      }



    } .elsewhen( stateCur === 6.U ){ 
      stateCur := 7.U

      //statusInit 
      mirrorReg.io.addrB  := 7.U
      mirrorReg.io.datawB := 1.U
      mirrorReg.io.enwB   := true.B

      ctrlInit    := false.B
      interrupt   := true.B

    } .elsewhen( stateCur === 7.U ){

    }
  }
}

trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
  val isSyncStart = ~RegNext( ctrlSynch, false.B) & ctrlSynch

  when( ctrlSynch ){
    when( isSyncStart ){
      stateCur := 0.U
      frame_info_update_en := false.B
      slave_type_num       := 0.U
      tx_start := false.B

    } .elsewhen( stateCur === 0.U ){ //statusSynch
      stateCur := 1.U

      mirrorReg.io.addrB  := 8.U
      mirrorReg.io.datawB := 0.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 1.U ){ 
      stateCur := 2.U

      //req slvnum
      mirrorReg.io.addrB  := 2.U
      mirrorReg.io.enrB   := true.B


    } .elsewhen( stateCur === 2.U ){ //slaveDataLength
      stateCur := 3.U

      //lock slvNum
      slvNum := mirrorReg.io.datarB

      mirrorReg.io.addrB  := 6.U
      mirrorReg.io.enrB   := true.B


    } .elsewhen( stateCur === 3.U ){
      stateCur := 4.U

      //lock slaveDataLength
      slaveDataLength := mirrorReg.io.datarB

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b01".U(2.W), slvNum )
      // slaveDataLength      := slaveDataLength

      tx_start := false.B
    } .elsewhen( stateCur === 4.U ){ // tx start
      stateCur := 5.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 5.U ){

      tx_start := false.B

      when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
        stateCur := 6.U

        //statusSync
        mirrorReg.io.addrB  := 8.U
        mirrorReg.io.datawB := 1.U
        mirrorReg.io.enwB   := true.B

        ctrlSynch   := false.B
        interrupt   := true.B
      }

    } .otherwise{

    }
  }

}


trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>

  val isTransStart = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)

  when(ctrlTransmit){
    when( isTransStart ){  //reset
      stateCur := 0.U

      frame_info_update_en := false.B
      slave_type_num       := 0.U

      tx_start := false.B
      

    }  .elsewhen( stateCur === 0.U ){ //statusTransmit
      stateCur := 1.U

      mirrorReg.io.addrB  := 9.U
      mirrorReg.io.datawB := 0.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 1.U ){ //slvnum
      stateCur := 2.U

      mirrorReg.io.addrB  := 2.U
      mirrorReg.io.enrB   := true.B

    } .elsewhen( stateCur === 2.U ){ //slaveDataLength
      stateCur := 3.U

      //lock slvNum
      slvNum := mirrorReg.io.datarB

      mirrorReg.io.addrB  := 6.U
      mirrorReg.io.enrB   := true.B

    } .elsewhen( stateCur === 3.U  ){ //setting
      stateCur := 4.U

      //lock slaveDataLength
      slaveDataLength := mirrorReg.io.datarB

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b10".U(2.W), slvNum )
      // slaveDataLength      := slaveDataLength

      tx_start := false.B
    } .elsewhen( stateCur === 4.U ){ // tx start
      stateCur := 5.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 5.U ){ //waiting  for busy drop

      tx_start := false.B

      when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
        stateCur := 6.U
      }

    } .elsewhen( stateCur === 6.U ){
      when( io.lvdsMst.upstream_crc_valid ){
        stateCur := 7.U

        //statusTransmit
        mirrorReg.io.addrB  := 9.U
        mirrorReg.io.datawB := 1.U
        mirrorReg.io.enwB   := true.B

        ctrlTransmit := false.B
        interrupt    := true.B
      }

    } .elsewhen( stateCur === 7.U ){  
      // stateCur := 8.U

    } .otherwise{

    }
  }




}

trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>

  val isUnicast = ctrlUnicast & ~RegNext(ctrlUnicast, false.B)

  when(ctrlUnicast){
    when( isUnicast ){  //reset
      stateCur := 0.U

      frame_info_update_en := false.B
      slave_type_num       := 0.U

      tx_start := false.B
      

    }  .elsewhen( stateCur === 0.U ){ //statusUnicast
      stateCur := 1.U

      mirrorReg.io.addrB  := 13.U
      mirrorReg.io.datawB := 0.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 1.U ){ //slvnum
      stateCur := 2.U

      mirrorReg.io.addrB  := 2.U
      mirrorReg.io.enrB   := true.B

    } .elsewhen( stateCur === 2.U ){ //slaveDataLength
      stateCur := 3.U

      //lock slvNum
      slvNum := mirrorReg.io.datarB

      mirrorReg.io.addrB  := 6.U
      mirrorReg.io.enrB   := true.B

    } .elsewhen( stateCur === 3.U  ){ //setting
      stateCur := 4.U

      //lock slaveDataLength
      slaveDataLength := mirrorReg.io.datarB

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b11".U(2.W), slvNum )
      // slaveDataLength      := slaveDataLength

      tx_start := false.B
    } .elsewhen( stateCur === 4.U ){ // tx start
      stateCur := 5.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 5.U ){ //waiting  for busy drop

      tx_start := false.B

      when( RegNext(io.lvdsMst.downstream_busy, false.B) & ~io.lvdsMst.downstream_busy ){
        stateCur := 6.U
      }

    } .elsewhen( stateCur === 6.U ){
      when( io.lvdsMst.upstream_crc_valid ){
        stateCur := 7.U

        //statusUnicast
        mirrorReg.io.addrB  := 13.U
        mirrorReg.io.datawB := 1.U
        mirrorReg.io.enwB   := true.B

        ctrlUnicast := false.B
        interrupt    := true.B
      }

    } .elsewhen( stateCur === 7.U ){  
      // stateCur := 8.U

    } .otherwise{

    }
  }

}


trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
  val shiftClosedLoopErr = ShiftRegisters( io.lvdsMst.closed_loop_err, 6, false.B, true.B )
  when( ~shiftClosedLoopErr(0) & io.lvdsMst.closed_loop_err ){

    //slvOffLine    := io.lvdsMst.link_err_location(5,0)
    mirrorReg.io.addrB  := 3.U
    mirrorReg.io.datawB := io.lvdsMst.link_err_location(5,0)
    mirrorReg.io.enwB   := true.B

  } .elsewhen( ~shiftClosedLoopErr(1) & shiftClosedLoopErr(0) ){
    //statusLinkErr := true.B
    mirrorReg.io.addrB  := 10.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B

  } .elsewhen( ~shiftClosedLoopErr(2) & shiftClosedLoopErr(1) ){
    mirrorReg.io.addrB  := 8.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B

    ctrlSynch   := false.B

  } .elsewhen( ~shiftClosedLoopErr(3) & shiftClosedLoopErr(2) ){
    mirrorReg.io.addrB  := 9.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B

    ctrlTransmit := false.B

  } .elsewhen( ~shiftClosedLoopErr(4) & shiftClosedLoopErr(3) ){
    mirrorReg.io.addrB  := 13.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B

    ctrlUnicast := false.B
  } .elsewhen( ~shiftClosedLoopErr(5) & shiftClosedLoopErr(4) ){
    interrupt     := true.B
  }




  when( io.lvdsMst.upstream_cdr_err ){
    // statusCDRErr := true.B
    mirrorReg.io.addrB  := 11.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B   
    interrupt     := true.B
  }

  when( io.lvdsMst.upstream_crc_valid & io.lvdsMst.upstream_crc_err ){
    // statusCRCErr := true.B
    mirrorReg.io.addrB  := 12.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B   
    interrupt     := true.B
  }

}

class BackBoardMst extends BackBoardMstLVDSBase
with BackBoardMstLVDSInit
with BackBoardMstLVDSSync
with BackBoardMstLVDSTransmit
with BackBoardMstLVDSUnicast
with BackBoardMstLVDSError{

  val addrr = RegInit(0.U(11.W))
  val addrw = RegInit(0.U(11.W))

  when( isTransStart | isUnicast ){
    addrw := 0.U
  } .elsewhen( io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){
    assert( (stateCur === 5.U) || (stateCur === 6.U) )
    addrw := addrw + 1.U
  }

  when( isTransStart | isUnicast ){
    addrr := 0.U
  } .elsewhen( io.lvdsMst.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){
    addrr := addrr + 1.U
  }

  mirrorDown.io.enwB := false.B
  mirrorDown.io.datawB := 0.U
  mirrorDown.io.enrB := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
  io.lvdsMst.tx_data_in := Mux( addrr.extract(0), mirrorDown.io.datarB(15,8), mirrorDown.io.datarB(7,0) )
  mirrorDown.io.addrB := addrr >> 1
  

  val rxData_msb = RegEnable( io.lvdsMst.rx_data_out, io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & ~addrw.extract(0) )
  mirrorUp.io.enrB   := false.B
  mirrorUp.io.enwB   := io.lvdsMst.rx_data_valid & (ctrlTransmit | ctrlUnicast) & addrw.extract(0)
  mirrorUp.io.datawB := (rxData_msb << 8) | io.lvdsMst.rx_data_out 
  mirrorUp.io.addrB := addrw >> 1
  
}