eb001/src/main/scala/backBoard/BackBoardMst.scala

package BACK

import chisel3._
import chisel3.util._




class FSMC_Port_Bundle extends Bundle{

  val ADIn  = Input(UInt(16.W))
  val ADOut = Output(UInt(16.W))
  val ADOEn = Output(Bool())
  val csn   = Input(Bool())
  val rdn   = Input(Bool())
  val wrn   = Input(Bool())
  val advn  = Input(Bool())
}


class BackBoardMstIO extends Bundle{
  val FSMC = new FSMC_Port_Bundle

val reset_calib = Input(Bool())
  val oser_pclk = Input(Bool()) //10M
  val oser_fclk = Input(Bool()) //50M
        val ides_pclk = Input(Bool()) //100M
  val ides_fclk = Input(Bool()) //400M

  val lvds_down_dout = Output(Bool())
  val lvds_up_din    = Input(Bool())

  val interrupt = Output(Bool())

  val testIO = Input(Bool())

}

class BackBoardMstBase extends Module{ //10M
  val io: BackBoardMstIO = IO(new BackBoardMstIO)

  val lvdsMst = Module(new Lvds_Bus_Master)
  val mirrorDown = Module(new MirrorSRAMDown())
  val mirrorUp   = Module(new MirrorSRAMUp())
  val mirrorReg  = Module(new MirrorSRAMDP())

    mirrorReg.io.addrB  := DontCare
    mirrorReg.io.datawB := DontCare
    mirrorReg.io.enwB   := false.B

  // val statusCDRErr  = RegInit( false.B )
  // val statusCRCErr  = RegInit( false.B )
  // val statusLinkErr = RegInit( false.B )
  // val statusSynch   = RegInit( false.B )
  // val statusInit    = RegInit( false.B )

  val ctrlTransmit = RegInit( false.B )
  val ctrlSynch    = RegInit( false.B )
  val ctrlInit     = RegInit( false.B )

  val ctrlFun = RegInit(0.U(8.W))

  val slvNum  = RegInit(0.U(6.W))
  // val slvOffLine = RegInit(0.U(6.W))
  // val linkNum = RegInit(0.U(7.W))
  // val testReg = RegInit("haa55".U(16.W))
  val interrupt = RegInit(false.B); io.interrupt := interrupt
  val slaveDataLength    = RegInit(((8/8)*32-1).U(8.W))

  lvdsMst.io.rst_n       := ~reset.asBool
  lvdsMst.io.reset_calib := io.reset_calib
  lvdsMst.io.oser_pclk   := io.oser_pclk
  lvdsMst.io.oser_fclk   := io.oser_fclk
  lvdsMst.io.ides_pclk   := io.ides_pclk
  lvdsMst.io.ides_fclk   := io.ides_fclk

  io.lvds_down_dout      := lvdsMst.io.lvds_down_dout
  lvdsMst.io.lvds_up_din := io.lvds_up_din





  mirrorDown.io.clockr := io.oser_pclk.asBool
  mirrorDown.io.clockw := io.ides_pclk.asBool //100M  

  mirrorUp.io.clockw := io.oser_pclk.asBool
  mirrorUp.io.clockr := io.ides_pclk.asBool   //100M

  mirrorReg.io.clockA := io.ides_pclk.asBool //100M
  mirrorReg.io.clockB := io.oser_pclk.asBool //10M

  when(interrupt === true.B){
    interrupt := false.B
  }


}




trait BackBoardMstFSMC{ this: BackBoardMstBase =>

  val isReqValid       = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
  val isAckReady       = RegInit(false.B)
  val wrRegAddr        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }  //100M
  val wrRegData        = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }  //100M

  withClockAndReset( io.ides_pclk.asClock, reset ){//100M



    io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn

    val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)

    val isAccessSRAM = ~latchAddr.extract(10) 
    val isAccessReg  =  latchAddr.extract(10)
    val activeAddr   =  latchAddr(9,0)
    // val regOut = Wire(UInt(16.W))




    mirrorDown.io.enw    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn
    mirrorDown.io.addrw  := activeAddr
    mirrorDown.io.dataw  := io.FSMC.ADIn

    mirrorUp.io.enr    := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn
    mirrorUp.io.addrr  := activeAddr

    mirrorReg.io.addrA  := activeAddr
    mirrorReg.io.datawA := io.FSMC.ADIn
    mirrorReg.io.enwA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
    // mirrorReg.io.enrA   := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn

    io.FSMC.ADOut   := Mux( isAccessReg, mirrorReg.io.datarA, mirrorUp.io.datar)

    // regOut := Mux1H(Seq(
    //   ( activeAddr === 0.U) -> 
    //     Cat(
    //       statusCDRErr ,
    //       statusCRCErr ,
    //       statusLinkErr,
    //       statusSynch  ,
    //       statusInit
    //     ),
    //   ( activeAddr === 1.U) -> ctrlFun,
    //   ( activeAddr === 2.U) -> slvNum,
    //   ( activeAddr === 3.U) -> slvOffLine,
    //   ( activeAddr === 4.U) -> testReg,
    //   ( activeAddr === 5.U) -> linkNum,
    //   ( activeAddr === 6.U) -> slaveDataLength,
    // ))



    // when( isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn ){
    //   isReqValid := true.B
    //   wrRegAddr        := activeAddr
    //   wrRegData        := io.FSMC.ADIn
    // }

    // when( isReqValid & isAckReady ){
    //   isReqValid := false.B
    // }



  }

  //10M
  when(~RegNext( io.testIO, false.B ) & io.testIO){

    mirrorReg.io.addrB  := 1.U
    mirrorReg.io.datawB := DontCare
    mirrorReg.io.enwB   := false.B

    when( mirrorReg.io.datarB === 0.U ){
      ctrlInit   := true.B
    }

    when( mirrorReg.io.datarB === 1.U ){
      
      ctrlSynch   := true.B
    }

    when( mirrorReg.io.datarB === 5.U ){
      ctrlTransmit := true.B      
    }
  }




  // when( isAckReady ){
  //   isAckReady := false.B
  // }

  // when( isReqValid ){
  //   isAckReady := true.B

  //   when( wrRegAddr === 0.U ){
  //     when( wrRegData.extract(4) ){
  //       statusCDRErr := false.B
  //     }
  //     when( wrRegData.extract(3) ){
  //       statusCRCErr := false.B
  //     }
  //     when( wrRegData.extract(2) ){
  //       statusLinkErr := false.B
  //     }
  //   }


  //   when( wrRegAddr === 1.U ){
  //     ctrlFun := wrRegData
  //   }

  //   when( wrRegAddr === 2.U ){
  //     slvNum := wrRegData
  //   }

  //   when( wrRegAddr === 4.U ){
  //     testReg := wrRegData
  //   }

  //   when( wrRegAddr === 6.U ){
  //     slaveDataLength := wrRegData
  //   }

  // }


}

abstract class BackBoardMstLVDSBase extends BackBoardMstBase 
with BackBoardMstFSMC
{


  val frame_info_update_en = RegInit(false.B)
  val slave_type_num       = RegInit(0.U(8.W))

  val tx_start             = RegInit(false.B)

  lvdsMst.io.frame_info_update_en := frame_info_update_en
  lvdsMst.io.slave_type_num       := slave_type_num
  lvdsMst.io.slave_data_length    := slaveDataLength
  lvdsMst.io.tx_start := tx_start

  val stateCur = RegInit(15.U(4.W))


}


trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>

  val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit
  val timeoutCnt = Reg(UInt(13.W))

  when(ctrlInit){
    when( isInitStart ){

      stateCur := 0.U
      frame_info_update_en := false.B
      slave_type_num       := 0.U
      tx_start := false.B
      
    } .elsewhen( stateCur === 0.U ){ //statusInit 
      stateCur := 1.U

      mirrorReg.io.addrB  := 7.U
      mirrorReg.io.datawB := 0.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 1.U ){
      stateCur := 2.U

      mirrorReg.io.addrB  := 2.U
      slvNum := mirrorReg.io.datarB
    } .elsewhen( stateCur === 2.U ){
      stateCur := 3.U

      mirrorReg.io.addrB  := 6.U
      slaveDataLength := mirrorReg.io.datarB
    }
    .elsewhen( stateCur === 3.U ){
      stateCur := 4.U

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b00".U(2.W), slvNum )
      slaveDataLength      := slaveDataLength

      tx_start := false.B
    } .elsewhen( stateCur === 4.U ){ // tx start
      stateCur := 5.U
      timeoutCnt := 0.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 5.U ){
      tx_start := false.B
      timeoutCnt := timeoutCnt + 1.U

      when( lvdsMst.io.slave_link_num_valid ){
        //linkNum 
        mirrorReg.io.addrB  := 5.U
        mirrorReg.io.datawB := lvdsMst.io.slave_link_num
        mirrorReg.io.enwB   := true.B


        stateCur := 6.U
        ctrlInit    := false.B
        interrupt   := true.B
      }

      when( timeoutCnt === 6000.U ){
        stateCur := 6.U

        //linkNum 
        mirrorReg.io.addrB  := 5.U
        mirrorReg.io.datawB := 0.U
        mirrorReg.io.enwB   := true.B

        ctrlInit    := false.B
        interrupt   := true.B
      }



    } .elsewhen( stateCur === 6.U ){ //statusInit 
      stateCur := 7.U

      mirrorReg.io.addrB  := 7.U
      mirrorReg.io.datawB := 1.U
      mirrorReg.io.enwB   := true.B

    } .elsewhen( stateCur === 7.U ){

    }
  }
}

trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
  val isSyncStart = ~RegNext( ctrlSynch, false.B) & ctrlSynch

  when( ctrlSynch ){
    when( isSyncStart ){
      stateCur := 0.U
      frame_info_update_en := false.B
      slave_type_num       := 0.U
      tx_start := false.B

    } .elsewhen( stateCur === 0.U ){ //statusSynch
      stateCur := 1.U

      mirrorReg.io.addrB  := 8.U
      mirrorReg.io.datawB := 0.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 1.U ){ //slvnum
      stateCur := 2.U

      mirrorReg.io.addrB  := 2.U
      slvNum := mirrorReg.io.datarB
    } .elsewhen( stateCur === 2.U ){ //slaveDataLength
      stateCur := 3.U

      mirrorReg.io.addrB  := 6.U
      slaveDataLength := mirrorReg.io.datarB
    } .elsewhen( stateCur === 3.U ){
      stateCur := 4.U

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b01".U(2.W), slvNum )
      slaveDataLength      := slaveDataLength

      tx_start := false.B
    } .elsewhen( stateCur === 4.U ){ // tx start
      stateCur := 5.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 5.U ){

      tx_start := false.B

      when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
        stateCur := 6.U
        ctrlSynch   := false.B
        interrupt   := true.B
      }

    } .elsewhen( stateCur === 6.U ){
      stateCur := 7.U
      mirrorReg.io.addrB  := 8.U
      mirrorReg.io.datawB := 1.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 7.U ){

    } .otherwise{

    }
  }

}


trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>

  val isTransStart = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)

  when(ctrlTransmit){
    when( isTransStart ){  //reset
      stateCur := 0.U

      frame_info_update_en := false.B
      slave_type_num       := 0.U

      tx_start := false.B
      

    }  .elsewhen( stateCur === 0.U ){ //statusTransmit
      stateCur := 1.U

      mirrorReg.io.addrB  := 9.U
      mirrorReg.io.datawB := 0.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 1.U ){ //slvnum
      stateCur := 2.U

      mirrorReg.io.addrB  := 2.U
      slvNum := mirrorReg.io.datarB
    } .elsewhen( stateCur === 2.U ){ //slaveDataLength
      stateCur := 3.U

      mirrorReg.io.addrB  := 6.U
      slaveDataLength := mirrorReg.io.datarB
    } .elsewhen( stateCur === 3.U  ){ //setting
      stateCur := 4.U

      frame_info_update_en := true.B
      slave_type_num       := Cat( "b10".U(2.W), slvNum )
      slaveDataLength      := slaveDataLength

      tx_start := false.B
    } .elsewhen( stateCur === 4.U ){ // tx start
      stateCur := 5.U

      frame_info_update_en := false.B
      tx_start := true.B

    } .elsewhen( stateCur === 5.U ){ //waiting  for busy drop

      tx_start := false.B

      when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
        stateCur := 6.U
      }

    } .elsewhen( stateCur === 6.U ){
      when( lvdsMst.io.upstream_crc_valid ){
        stateCur := 7.U
        ctrlTransmit := false.B
        interrupt    := true.B
      }

    } .elsewhen( stateCur === 7.U ){  //statusTransmit
      stateCur := 8.U
      mirrorReg.io.addrB  := 9.U
      mirrorReg.io.datawB := 1.U
      mirrorReg.io.enwB   := true.B
    } .elsewhen( stateCur === 8.U ){
    } .otherwise{

    }
  }


  val addrr = RegInit(0.U(11.W))
  val addrw = RegInit(0.U(11.W))

  when( isTransStart ){
    addrw := 0.U
  } .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){
    assert( (stateCur === 5.U) || (stateCur === 6.U) )
    addrw := addrw + 1.U
  }

  when( isTransStart ){
    addrr := 0.U
  } .elsewhen( lvdsMst.io.tx_data_ready & ctrlTransmit){
    addrr := addrr + 1.U
  }

  mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & ctrlTransmit
  lvdsMst.io.tx_data_in := mirrorDown.io.datar
  mirrorDown.io.addrr := addrr
  
  mirrorUp.io.enw    := lvdsMst.io.rx_data_valid & ctrlTransmit
  mirrorUp.io.dataw := lvdsMst.io.rx_data_out
  mirrorUp.io.addrw := addrw

}

trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
  when( lvdsMst.io.closed_loop_err ){

    //slvOffLine    := lvdsMst.io.link_err_location(5,0)
    mirrorReg.io.addrB  := 3.U
    mirrorReg.io.datawB := lvdsMst.io.link_err_location(5,0)
    mirrorReg.io.enwB   := true.B    

  } .elsewhen( RegNext(lvdsMst.io.closed_loop_err, false.B)){

    //statusLinkErr := true.B
    mirrorReg.io.addrB  := 10.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B   

    interrupt     := true.B
  }

  when( lvdsMst.io.upstream_cdr_err ){
    // statusCDRErr := true.B
    mirrorReg.io.addrB  := 11.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B   
    interrupt     := true.B
  }

  when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
    // statusCRCErr := true.B
    mirrorReg.io.addrB  := 12.U
    mirrorReg.io.datawB := 1.U
    mirrorReg.io.enwB   := true.B   
    interrupt     := true.B
  }

}

class BackBoardMst extends BackBoardMstLVDSBase
with BackBoardMstLVDSInit
with BackBoardMstLVDSSync
with BackBoardMstLVDSTransmit
with BackBoardMstLVDSError