Files
eb001/tb/shinTest/ShinTopSpiTb.v

774 lines
21 KiB
Coq
Raw Normal View History

2025-05-12 15:41:11 +08:00
`timescale 1 ns / 1 ps
module ShinTopSpiTb(
);
reg clock;
reg reset;
reg clk8x;
wire [3:0] dDat_w;
wire [3:0] uDat_w;
wire spi_sck;
wire spi_mosi;
2025-05-17 12:20:07 +08:00
wire [4:0] spi_miso;
2025-05-14 16:26:20 +08:00
reg [14:0] spi_csn;
wire qspi_sck;
wire [3:0] qspi_mosi;
2025-05-17 12:20:07 +08:00
wire [40-1:0] qspi_miso;
2025-05-12 15:41:11 +08:00
2025-05-13 10:31:35 +08:00
wire isResp;
2025-05-12 15:41:11 +08:00
2025-05-16 18:07:22 +08:00
integer spidata_file;
integer c_line;
2025-05-16 18:07:22 +08:00
2025-05-12 15:41:11 +08:00
ShinTop s_ShinTop_Mst(
.clock(clock),
.reset(reset),
.io_clk8x(clk8x),
.io_dDatIn(1'b0),
.io_dDatOut(dDat_w[0]),
.io_uDatIn(uDat_w[0]),
.io_uDatOut(),
2025-05-14 16:26:20 +08:00
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_iqspi_miso(qspi_miso[3:0]),
2025-05-14 16:26:20 +08:00
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[0]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
2025-05-17 12:20:07 +08:00
.io_ospi_miso(spi_miso[0]),
2025-05-14 16:26:20 +08:00
.io_ospi_csn (spi_csn[5]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_oqspi_miso(qspi_miso[4*5+3:4*5]),
2025-05-14 16:26:20 +08:00
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[10]),
2025-05-12 15:41:11 +08:00
2025-05-13 10:31:35 +08:00
.io_rsp_valid(isResp),
.io_rsp_bits_isError()
// .io_rsp_bits_length()
2025-05-12 15:41:11 +08:00
);
ShinTop s_ShinTop_slv0(
.clock(clock),
.reset(reset),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[0]),
.io_dDatOut(dDat_w[1]),
.io_uDatIn(uDat_w[1]),
.io_uDatOut(uDat_w[0]),
2025-05-14 16:26:20 +08:00
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_iqspi_miso(qspi_miso[4*1+3:4*1]),
2025-05-14 16:26:20 +08:00
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[1]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
2025-05-17 12:20:07 +08:00
.io_ospi_miso(spi_miso[1]),
2025-05-14 16:26:20 +08:00
.io_ospi_csn (spi_csn[6]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_oqspi_miso(qspi_miso[4*6+3:4*6]),
2025-05-14 16:26:20 +08:00
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[11]),
2025-05-12 15:41:11 +08:00
.io_rsp_valid(),
.io_rsp_bits_isError()
// .io_rsp_bits_length()
2025-05-12 15:41:11 +08:00
);
ShinTop s_ShinTop_slv1(
.clock(clock),
.reset(reset),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[1]),
.io_dDatOut(dDat_w[2]),
.io_uDatIn(uDat_w[2]),
.io_uDatOut(uDat_w[1]),
2025-05-14 16:26:20 +08:00
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_iqspi_miso(qspi_miso[4*2+3:4*2]),
2025-05-14 16:26:20 +08:00
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[2]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
2025-05-17 12:20:07 +08:00
.io_ospi_miso(spi_miso[2]),
2025-05-14 16:26:20 +08:00
.io_ospi_csn (spi_csn[7]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_oqspi_miso(qspi_miso[4*7+3:4*7]),
2025-05-14 16:26:20 +08:00
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[12]),
2025-05-12 15:41:11 +08:00
.io_rsp_valid(),
.io_rsp_bits_isError()
// .io_rsp_bits_length()
2025-05-12 15:41:11 +08:00
);
ShinTop s_ShinTop_slv2(
.clock(clock),
.reset(reset),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[2]),
.io_dDatOut(dDat_w[3]),
.io_uDatIn(uDat_w[3]),
.io_uDatOut(uDat_w[2]),
2025-05-14 16:26:20 +08:00
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_iqspi_miso(qspi_miso[4*3+3:4*3]),
2025-05-14 16:26:20 +08:00
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[3]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
2025-05-17 12:20:07 +08:00
.io_ospi_miso(spi_miso[3]),
2025-05-14 16:26:20 +08:00
.io_ospi_csn (spi_csn[8]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_oqspi_miso(qspi_miso[4*8+3:4*8]),
2025-05-14 16:26:20 +08:00
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[13]),
2025-05-12 15:41:11 +08:00
.io_rsp_valid(),
.io_rsp_bits_isError()
// .io_rsp_bits_length()
2025-05-12 15:41:11 +08:00
);
ShinTop s_ShinTop_slv3(
.clock(clock),
.reset(reset),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[3]),
.io_dDatOut(),
.io_uDatIn(1'b0),
.io_uDatOut(uDat_w[3]),
2025-05-14 16:26:20 +08:00
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_iqspi_miso(qspi_miso[4*4+3:4*4]),
2025-05-14 16:26:20 +08:00
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[4]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
2025-05-17 12:20:07 +08:00
.io_ospi_miso(spi_miso[4]),
2025-05-14 16:26:20 +08:00
.io_ospi_csn (spi_csn[9]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
2025-05-17 12:20:07 +08:00
.io_oqspi_miso(qspi_miso[4*9+3:4*9]),
2025-05-14 16:26:20 +08:00
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[14]),
2025-05-12 15:41:11 +08:00
.io_rsp_valid(),
.io_rsp_bits_isError()
// .io_rsp_bits_length()
2025-05-12 15:41:11 +08:00
);
initial begin
clock = 0;
clk8x = 0;
reset = 0;
2025-05-14 16:26:20 +08:00
spi_csn = ~15'b0;
2025-05-12 15:41:11 +08:00
#100
reset <= 1;
#240
reset <= 0;
2025-05-19 08:32:05 +08:00
#20000000
2025-05-12 15:41:11 +08:00
$display("Time Out !!!");
2025-05-16 18:07:22 +08:00
$fclose(spidata_file);
2025-05-12 15:41:11 +08:00
$stop;
end
initial begin
forever begin #20 clk8x <= ~clk8x; end
2025-05-12 15:41:11 +08:00
end
initial begin
forever begin #80 clock <= ~clock; end
end
initial
begin
2025-05-16 18:07:22 +08:00
spidata_file = $fopen("spi_trans_data.txt", "w");
if (!spidata_file) $display("文件打开失败");
2025-05-12 15:41:11 +08:00
$dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, ShinTopSpiTb);//tb模块名称
end
`define SCKFRE #640
2025-05-12 15:41:11 +08:00
reg sck = 0;
2025-05-12 15:41:11 +08:00
initial begin
forever begin
`SCKFRE sck <= ~sck;
end
2025-05-12 15:41:11 +08:00
end
2025-05-14 16:26:20 +08:00
assign spi_sck = sck;
assign qspi_sck = sck;
2025-05-12 15:41:11 +08:00
reg [7:0] txBuf[0:2047];
reg [7:0] rxBuf[0:2047];
2025-05-19 14:13:47 +08:00
reg [7:0] exChangeRego;
reg [7:0] exChangeRegi;
2025-05-14 16:26:20 +08:00
2025-05-19 14:13:47 +08:00
assign spi_mosi = exChangeRego[7];
assign qspi_mosi = exChangeRego[7:4];
2025-05-17 12:20:07 +08:00
wire [3:0] qspi_mux_miso =
( qspi_miso[4*0+3:4*0] & ~{4{spi_csn[ 0]}}) |
( qspi_miso[4*1+3:4*1] & ~{4{spi_csn[ 1]}}) |
( qspi_miso[4*2+3:4*2] & ~{4{spi_csn[ 2]}}) |
( qspi_miso[4*3+3:4*3] & ~{4{spi_csn[ 3]}}) |
( qspi_miso[4*4+3:4*4] & ~{4{spi_csn[ 4]}}) |
( qspi_miso[4*5+3:4*5] & ~{4{spi_csn[10]}}) |
( qspi_miso[4*6+3:4*6] & ~{4{spi_csn[11]}}) |
( qspi_miso[4*7+3:4*7] & ~{4{spi_csn[12]}}) |
( qspi_miso[4*8+3:4*8] & ~{4{spi_csn[13]}}) |
( qspi_miso[4*9+3:4*9] & ~{4{spi_csn[14]}});
wire spi_mux_miso =
( spi_miso[0] & ~spi_csn[5] ) |
( spi_miso[1] & ~spi_csn[6] ) |
( spi_miso[2] & ~spi_csn[7] ) |
( spi_miso[3] & ~spi_csn[8] ) |
( spi_miso[4] & ~spi_csn[9] );
2025-05-12 15:41:11 +08:00
reg isReq = 0;
reg isBusy = 0;
reg [11:0] length;
reg [7:0] idx;
2025-05-12 15:41:11 +08:00
reg [11:0] transCnt;
reg [11:0] byteCnt;
2025-05-13 10:31:35 +08:00
reg [2:0] bitCnt;
2025-05-12 15:41:11 +08:00
2025-05-13 10:31:35 +08:00
always @(posedge clock) begin
if( isReq & sck == 0 ) begin
isBusy <= #5 1'b1;
transCnt <= #5 0;
2025-05-14 16:26:20 +08:00
byteCnt <= #5 ~12'b0;
bitCnt <= #5 ~3'b0;
spi_csn[idx] <= #5 1'b0;
2025-05-19 14:13:47 +08:00
exChangeRego <= txBuf[0];
end
2025-05-13 10:31:35 +08:00
end
2025-05-13 10:31:35 +08:00
2025-05-14 16:26:20 +08:00
wire isQspi = (idx >= 0 && idx <= 4) || idx >= 10;
2025-05-16 18:07:22 +08:00
wire [11:0] nextByteCnt = byteCnt + 1;
2025-05-14 16:26:20 +08:00
2025-05-19 14:13:47 +08:00
//输出
always @(negedge sck) begin
if( isBusy ) begin
if( &bitCnt ) begin
2025-05-20 15:10:42 +08:00
exChangeRego <= txBuf[nextByteCnt];
2025-05-19 14:13:47 +08:00
end else begin
2025-05-20 15:10:42 +08:00
exChangeRego <= isQspi ? exChangeRego << 4 : exChangeRego << 1;
2025-05-19 14:13:47 +08:00
end
end
end
//输入
2025-05-13 10:31:35 +08:00
always @(posedge sck) begin
if( isBusy ) begin
2025-05-14 16:26:20 +08:00
if( transCnt <= length ) begin
if( isQspi ) begin
bitCnt <= ~bitCnt;
end else begin
bitCnt <= bitCnt + 1;
end
2025-05-13 10:31:35 +08:00
2025-05-14 16:26:20 +08:00
if( &bitCnt ) begin
byteCnt <= byteCnt +1;
2025-05-13 10:31:35 +08:00
transCnt <= transCnt + 1;
2025-05-17 12:20:07 +08:00
if( txBuf[2] === 1 & nextByteCnt >= 4) begin
2025-05-19 15:04:15 +08:00
rxBuf[byteCnt] <= exChangeRegi;
2025-05-19 14:13:47 +08:00
$display("spi read out %x", exChangeRegi);
2025-05-17 12:20:07 +08:00
end
if( txBuf[2] === 1 & nextByteCnt >= 3) begin
2025-05-19 14:13:47 +08:00
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
2025-05-17 12:20:07 +08:00
end else begin
2025-05-19 14:13:47 +08:00
exChangeRegi <= 0;
2025-05-17 12:20:07 +08:00
end
end else begin
2025-05-20 17:21:02 +08:00
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
2025-05-12 15:41:11 +08:00
end
end else begin
isBusy <= #5 1'b0;
spi_csn[idx] <= #5 1'b1;
2025-05-12 15:41:11 +08:00
end
end
end
2025-05-16 18:07:22 +08:00
//mst slv0~slv3的 内部qspi调用即设置
//sidx为0~4外部spi为5~9外部qspi为10~15
task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx );
begin
txBuf[0] <= saddress[7:0];
txBuf[1] <= saddress[15:8];
txBuf[2] <= scmd;
2025-05-13 10:31:35 +08:00
length <= slength + 3;
idx <= sidx;
#5
@(negedge sck)
isReq <= 1;
@(posedge sck) #5
isReq <= 0;
2025-05-13 10:31:35 +08:00
@( negedge isBusy) #1000
2025-05-16 18:07:22 +08:00
begin
//$fwrite(spidata_file, "------------%5t------------\n", $time);
$fwrite(spidata_file, "T:%2tns \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n",
$time/1000, ((sidx >= 5)? ((sidx >= 10)? (sidx - 10):(sidx - 5)):sidx), txBuf[1], txBuf[0],
((txBuf[2] == 0)? "Write":" Read"), slength);
2025-05-19 08:32:05 +08:00
for (integer i=0; i<slength; i++) begin
if (scmd == 0) begin
$fwrite(spidata_file, "%02h ", txBuf[i + 3]);
2025-05-19 08:32:05 +08:00
end else begin
$fwrite(spidata_file, "%02h ", rxBuf[i + 3]);
2025-05-19 08:32:05 +08:00
end
c_line = 0;
if ((i+1)%16 == 0) begin
$fwrite(spidata_file, "\n");
c_line = 1;
2025-05-16 18:07:22 +08:00
end
end
2025-05-19 08:32:05 +08:00
if (c_line == 0) begin
$fwrite(spidata_file, "\n");
end
c_line = 0;
2025-05-16 18:07:22 +08:00
end
2025-05-12 15:41:11 +08:00
end
2025-05-12 15:41:11 +08:00
endtask
2025-05-16 18:07:22 +08:00
`define INTERFACE_IDX 0 //internal spi
`define IF_IDX(idx) ((`INTERFACE_IDX)+(idx))
`define IF_IQSPI(idx) ((idx))
`define IF_OQSPI(idx) ((10) + (idx))
`define IF_OSPI(idx) ((5) + (idx))
2025-05-16 18:07:22 +08:00
`define SPI_WRITE 8'h0
`define SPI_READ 8'h1
2025-05-12 15:41:11 +08:00
/*---------------------------------------------------------------------------------------------------------
测试用例1
---------------------------------------------------------------------------------------------------------*/
2025-05-12 15:41:11 +08:00
initial begin
#1000
2025-05-16 18:07:22 +08:00
$fdisplay(spidata_file, "测试用例1-从IP中读取寄存器上电后的寄存器期望值为0");
spi_trans( (16'h00), (`SPI_READ), (64), (`IF_IQSPI(0)) );
2025-05-19 08:32:05 +08:00
spi_trans( (16'h00), (`SPI_READ), (64), (`IF_IQSPI(1)) );
spi_trans( (16'h00), (`SPI_READ), (64), (`IF_IQSPI(2)) );
spi_trans( (16'h00), (`SPI_READ), (64), (`IF_IQSPI(3)) );
spi_trans( (16'h00), (`SPI_READ), (64), (`IF_IQSPI(4)) );
if ((`INTERFACE_IDX) == 5) begin
$fdisplay(spidata_file, "\n\n从内部QSPI配置使用外部的SPI接口访问EasyBus");
txBuf[0+3] = 8'h01;
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(0)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(1)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(2)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(3)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(4)) );
end else if ((`INTERFACE_IDX) == 10) begin
$fdisplay(spidata_file, "\n\n从内部QSPI配置使用外部的QSPI接口访问EasyBus");
txBuf[0+3] = 8'h02;
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(0)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(1)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(2)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(3)) );
spi_trans( (16'h09), (`SPI_WRITE), (1), (`IF_IQSPI(4)) );
end else begin
$fdisplay(spidata_file, "\n\n从内部QSPI接口访问EasyBus");
end
2025-05-16 18:07:22 +08:00
/*---------------------------------------------------------------------------------------------------------
测试用例2
---------------------------------------------------------------------------------------------------------*/
2025-05-12 15:41:11 +08:00
//设置主站从站
2025-05-16 18:07:22 +08:00
$fdisplay(spidata_file, "\n\n测试用例2-设置IP为主站或从站并读取设置结果期望0主1~4从");
txBuf[0+3] = 8'h01;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h00), (`SPI_WRITE), (1), (`IF_IDX(0)) );
2025-05-12 15:41:11 +08:00
#1000
txBuf[0+3] = 8'h02;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h0), (`SPI_WRITE), (1), (`IF_IDX(1)) );
2025-05-12 15:41:11 +08:00
#1000
2025-05-16 18:07:22 +08:00
spi_trans( (16'h0), (`SPI_WRITE), (1), (`IF_IDX(2)) );
2025-05-12 15:41:11 +08:00
#1000
2025-05-16 18:07:22 +08:00
spi_trans( (16'h0), (`SPI_WRITE), (1), (`IF_IDX(3)) );
2025-05-12 15:41:11 +08:00
#1000
2025-05-16 18:07:22 +08:00
spi_trans( (16'h0), (`SPI_WRITE), (1), (`IF_IDX(4)) );
$fdisplay(spidata_file, "--->>>设置完毕,检查接口寄存器");
2025-05-16 18:07:22 +08:00
spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(0)) );
spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(1)) );
spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(2)) );
spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(3)) );
spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(4)) );
2025-05-12 15:41:11 +08:00
/*---------------------------------------------------------------------------------------------------------
测试用例3
---------------------------------------------------------------------------------------------------------*/
2025-05-12 15:41:11 +08:00
//嗅探
#10000
2025-05-16 18:07:22 +08:00
$fdisplay(spidata_file, "\n\n测试用例3-发送嗅探包,需要在波形文件里检查");
2025-05-12 15:41:11 +08:00
begin
$fdisplay(spidata_file, "--->>>嗅探前,检查链路状态寄存器");
//spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(0)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(1)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(2)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(3)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(4)) );
2025-05-16 18:07:22 +08:00
$fdisplay(spidata_file, "--->>>嗅探");
//设置SM1在写入0x4 len 触发enq
//设置SM0在读出0x4 len 触发deq
txBuf[0+3] = 8'h04;
txBuf[1+3] = 8'h00;
spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
2025-05-12 15:41:11 +08:00
//无子报文
`include "detect_pkt.vh"
2025-05-16 18:07:22 +08:00
spi_trans( (16'h1000), (`SPI_WRITE), (4), (`IF_IDX(0)) ); //写入SM1
2025-05-12 15:41:11 +08:00
//发布请求
txBuf[0+3] = 8'h01;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
2025-05-13 10:31:35 +08:00
@(posedge isResp) #5 begin end
rxBuf[0+3] = 0;
spi_trans( (16'h803), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址将fifo弹出
2025-05-12 15:41:11 +08:00
end
// 顺序索引
2025-05-20 11:48:49 +08:00
//#50000
2025-05-12 15:41:11 +08:00
#50000
#50000
$fdisplay(spidata_file, "--->>>嗅探后,检查链路状态寄存器");
//spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(0)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(1)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(2)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(3)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(4)) );
2025-05-16 18:07:22 +08:00
/*---------------------------------------------------------------------------------------------------------
2025-05-20 16:03:20 +08:00
测试用例4
---------------------------------------------------------------------------------------------------------*/
2025-05-16 18:07:22 +08:00
$fdisplay(spidata_file, "\n\n测试用例4-设置顺序索引");
2025-05-15 14:57:58 +08:00
$display("index @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp);
2025-05-12 15:41:11 +08:00
begin
$fdisplay(spidata_file, "--->>>设置顺序地址前,检查顺序地址");
2025-05-16 18:07:22 +08:00
//spi_trans( (16'h0010), (`SPI_READ), (5), (`IF_IDX(0)) );
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(1)) );
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(2)) );
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(3)) );
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(4)) );
2025-05-12 15:41:11 +08:00
$fdisplay(spidata_file, "--->>>设置顺序地址");
//设置SM1在写入0xe len触发enq
txBuf[0+3] = 8'h0e;
txBuf[1+3] = 8'h00;
spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
2025-05-12 15:41:11 +08:00
txBuf[0+3] = 8'h00;
txBuf[1+3] = 8'ha0;//heeader length 10
txBuf[2+3] = 8'h00;
txBuf[3+3] = 8'h00;
2025-05-12 15:41:11 +08:00
//子报文
//设置顺序地址
txBuf[4+3] = 8'h0; //设备索引
txBuf[5+3] = 8'h0; //设备索引类型
txBuf[6+3] = $random; //地址
txBuf[7+3] = $random; //地址
txBuf[8+3] = 8'hd0; //命令d 负载长度2
txBuf[9+3] = 8'd02; //负载长度2
txBuf[10+3] = 8'h0; //工作计数0
txBuf[11+3] = 8'h0; //工作计数0
txBuf[12+3] = 8'h0; //负载
txBuf[13+3] = 8'h0; //负载
2025-05-16 18:07:22 +08:00
spi_trans( (16'h1000), (`SPI_WRITE), (14), (`IF_IDX(0)) ); //写入SM1
2025-05-12 15:41:11 +08:00
//发布请求
txBuf[0+3] = 8'h01;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
2025-05-13 10:31:35 +08:00
@(posedge isResp) #5 begin end
rxBuf[0+3] = 0;
spi_trans( (16'h80D), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址将fifo弹出
2025-05-12 15:41:11 +08:00
end
2025-05-17 12:20:07 +08:00
//测试
2025-05-19 15:07:12 +08:00
spi_trans( (16'hc0), (`SPI_READ), (6), (`IF_IDX(3)) );
spi_trans( (16'h0a), (`SPI_READ), (2), (`IF_IDX(1)) );
spi_trans( (16'h0a), (`SPI_READ), (2), (`IF_IDX(2)) );
spi_trans( (16'h0a), (`SPI_READ), (2), (`IF_IDX(3)) );
spi_trans( (16'h0a), (`SPI_READ), (2), (`IF_IDX(4)) );
2025-05-17 12:20:07 +08:00
2025-05-12 15:41:11 +08:00
//读写
#50000
#50000
$fdisplay(spidata_file, "--->>>设置顺序地址后,检查顺序地址");
2025-05-16 18:07:22 +08:00
//spi_trans( (16'h0010), (`SPI_READ), (5), (`IF_IDX(0)) );
2025-05-17 12:35:44 +08:00
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(1)) );
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(2)) );
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(3)) );
spi_trans( (16'h0000), (`SPI_READ), (16), (`IF_IDX(4)) );
2025-05-16 18:07:22 +08:00
2025-05-20 16:03:20 +08:00
/*---------------------------------------------------------------------------------------------------------
测试用例5
---------------------------------------------------------------------------------------------------------*/
2025-05-20 11:48:49 +08:00
//嗅探
#10000
$fdisplay(spidata_file, "\n\n测试用例5-发送嗅探包,需要在波形文件里检查");
begin
$fdisplay(spidata_file, "--->>>嗅探前,检查链路状态寄存器");
//spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(0)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(1)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(2)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(3)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(4)) );
$fdisplay(spidata_file, "--->>>嗅探");
//设置SM1在写入0x3地址触发enq
txBuf[0+3] = 8'h03;
txBuf[1+3] = 8'h00;
spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
2025-05-20 11:48:49 +08:00
//无子报文
`include "detect_pkt.vh"
spi_trans( (16'h1000), (`SPI_WRITE), (4), (`IF_IDX(0)) ); //写入SM1
//发布请求
txBuf[0+3] = 8'h04;
txBuf[1+3] = 8'h00;
spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
txBuf[0+3] = 8'h01;
spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
@(posedge isResp) #5 begin end
end
// 顺序索引
//#50000
#50000
#50000
$fdisplay(spidata_file, "--->>>嗅探后,检查链路状态寄存器");
//spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(0)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(1)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(2)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(3)) );
spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(4)) );
2025-05-20 16:03:20 +08:00
/*---------------------------------------------------------------------------------------------------------
测试用例6
---------------------------------------------------------------------------------------------------------*/
2025-05-20 11:48:49 +08:00
#50000
#50000
$fdisplay(spidata_file, "\n\n测试用例6-交换数据");
$display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp);
2025-05-12 15:41:11 +08:00
begin
//设置SM1在写入516 len触发enq
txBuf[0+3] = 8'h04;
txBuf[1+3] = 8'h02;
spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
2025-05-12 15:41:11 +08:00
`include "seq_pkt.vh"
2025-05-16 18:07:22 +08:00
spi_trans( (16'h1000), (`SPI_WRITE), (516), (`IF_IDX(0)) ); //写入SM1
2025-05-12 15:41:11 +08:00
//发布请求
txBuf[0+3] = 8'h01;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
2025-05-13 10:31:35 +08:00
@(posedge isResp) #5 begin end
2025-05-12 15:41:11 +08:00
end
spi_trans( (16'ha03), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址将fifo弹出
2025-05-12 15:41:11 +08:00
2025-05-20 16:03:20 +08:00
/*---------------------------------------------------------------------------------------------------------
测试用例7
测试 同步(sync) 同步输出 (sync_out)
---------------------------------------------------------------------------------------------------------*/
2025-05-12 15:41:11 +08:00
// 同步
#90000
#90000
#90000
#90000
#90000
#90000
#90000
#90000
#90000
#90000
#90000
#90000
#90000
#90000
2025-05-15 14:57:58 +08:00
$display("sync @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp);
2025-05-20 16:03:20 +08:00
$fdisplay(spidata_file, "\n\n测试用例-测试同步(sync)和同步输出(sync_out)");
2025-05-12 15:41:11 +08:00
begin
//设置SM1在写入 0x18 len触发enq
txBuf[0+3] = 8'h18;
txBuf[1+3] = 8'h00;
spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
2025-05-12 15:41:11 +08:00
`include "sync_pkt.vh"
2025-05-16 18:07:22 +08:00
spi_trans( (16'h1000), (`SPI_WRITE), (24), (`IF_IDX(0)) ); //写入SM1
2025-05-12 15:41:11 +08:00
2025-05-15 14:57:58 +08:00
//写入替换时间戳替换地址
txBuf[0+3] = 8'h0c;
txBuf[1+3] = 8'hc0;
2025-05-17 12:27:31 +08:00
spi_trans( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(0)) ); //写入替换时间戳替换地址寄存器
2025-05-12 15:41:11 +08:00
//发布请求
txBuf[0+3] = 8'h01;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
@(posedge isResp) #5 begin
spi_trans( (16'h817), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址将fifo弹出
end
2025-05-12 15:41:11 +08:00
2025-05-16 16:05:38 +08:00
//清除替换时间戳替换地址
txBuf[0+3] = 8'h00;
txBuf[1+3] = 8'h00;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h25), (`SPI_WRITE), (2), (`IF_IDX(0)) ); //清除替换时间戳替换地址寄存器
2025-05-16 16:05:38 +08:00
//设置SM1在写入52 len触发enq
txBuf[0+3] = 8'd52;
2025-05-16 16:05:38 +08:00
txBuf[1+3] = 8'h00;
spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
2025-05-16 16:05:38 +08:00
`include "sync_sig_pkt.vh"
2025-05-16 18:07:22 +08:00
spi_trans( (16'h1000), (`SPI_WRITE), (52), (`IF_IDX(0)) ); //写入SM1
2025-05-16 16:05:38 +08:00
//发布请求
txBuf[0+3] = 8'h01;
2025-05-16 18:07:22 +08:00
spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
2025-05-16 16:05:38 +08:00
@(posedge isResp) #5 begin end
spi_trans( (16'h833), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址将fifo弹出
2025-05-12 15:41:11 +08:00
end
2025-05-20 16:03:20 +08:00
2025-05-16 16:42:07 +08:00
//清脉冲
txBuf[0+3] = 0; //负载0x122 sync0脉冲宽度
txBuf[1+3] = 0; //负载0x123
txBuf[2+3] = 0; //负载0x124 sync1脉冲宽度
txBuf[3+3] = 0; //负载0x125
txBuf[4+3] = 0; //负载0x126 sync2脉冲宽度
txBuf[5+3] = 0; //负载0x127
txBuf[6+3] = 0; //负载0x128 sync3脉冲宽度
txBuf[7+3] = 0; //负载0x129
2025-05-16 18:07:22 +08:00
spi_trans( (16'h0122), (`SPI_WRITE), (8), (`IF_IDX(2)) ); //slv2
2025-05-12 15:41:11 +08:00
end
endmodule