2024-10-29 17:32:17 +08:00
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#include <stdint.h>
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// #include "uart.h"
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// #include "gpio.h"
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// #include "timer.h"
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2025-01-16 16:34:48 +08:00
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#include "tl2cdr.h"
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2025-02-10 00:08:30 +08:00
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#include "system_cfg.h"
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2025-02-10 14:38:49 +08:00
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#include "halfLvdsMacSvr.h"
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#include "sysDef.h"
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2024-11-05 17:48:34 +08:00
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2025-02-10 14:38:49 +08:00
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#ifdef __riscv_i
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#define USING_POLL_STRATEGY
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#endif
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2025-01-27 22:25:39 +08:00
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2025-02-10 00:03:16 +08:00
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volatile uint32_t *const plic_priority = (uint32_t *)(0xc000000U);
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2025-01-15 15:44:29 +08:00
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2025-01-16 16:34:48 +08:00
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volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
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volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
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2025-01-15 15:44:29 +08:00
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2025-01-16 16:34:48 +08:00
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volatile uint32_t *plic_threshold_0 = (uint32_t*)( 0xc000000U + 0X200000 );
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volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
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2025-01-15 15:44:29 +08:00
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2025-02-10 14:38:49 +08:00
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static void error();
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static uint32_t init_plic(void);
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2025-01-15 15:44:29 +08:00
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2025-02-10 14:38:49 +08:00
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void main()
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{
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init_plic();
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2025-01-15 15:44:29 +08:00
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2025-02-10 14:38:49 +08:00
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//复位脉冲
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*tx0_softReset = 1;
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*tx1_softReset = 1;
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*rx0_softReset = 1;
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*rx1_softReset = 1;
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2025-01-15 15:44:29 +08:00
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2025-01-16 16:34:48 +08:00
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2025-02-10 14:38:49 +08:00
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//tx0 下行
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//tx1 上行
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//rx0 下行
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//rx1 上行
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#ifdef USING_POLL_STRATEGY
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//使用查询策略 POLL_STRATEGY 操作 half lvds mac
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HLM_poll(WORKMODE_SLAVE);
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2025-01-15 15:44:29 +08:00
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2025-02-10 14:38:49 +08:00
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#else
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//使用中断策略操作half lvds mac
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HLM_work_with_isr(WORKMODE_SLAVE);
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#endif
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while (1);
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}
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void error() {
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while(1);
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}
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2025-02-10 00:03:16 +08:00
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2025-02-10 14:38:49 +08:00
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uint32_t init_plic(void)
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{
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2025-02-10 00:03:16 +08:00
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/*初始化plic*/
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*plic_enable_0_31 = 1 << CDR_INT_TX0END
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| 1 << CDR_INT_TX1END
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| 1 << CDR_INT_RX0ERROR
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| 1 << CDR_INT_RX1ERROR
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| 1 << CDR_INT_RX0START
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| 1 << CDR_INT_RX1START
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| 1 << CDR_INT_RX0END
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| 1 << CDR_INT_RX1END
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//| 1 << CDR_INT_TX0_FIFO_DEQ
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//| 1 << CDR_INT_TX1_FIFO_DEQ
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| 1 << CDR_INT_RX0_FIFO_ENQ
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| 1 << CDR_INT_RX1_FIFO_ENQ
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;
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plic_priority[CDR_INT_TX0END] = 1;
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plic_priority[CDR_INT_TX1END] = 1;
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plic_priority[CDR_INT_RX0ERROR] = 1;
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plic_priority[CDR_INT_RX1ERROR] = 1;
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plic_priority[CDR_INT_RX0START] = 1;
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plic_priority[CDR_INT_RX1START] = 1;
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plic_priority[CDR_INT_RX0END] = 1;
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plic_priority[CDR_INT_RX1END] = 1;
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plic_priority[CDR_INT_TX0_FIFO_DEQ] = 1;
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plic_priority[CDR_INT_TX1_FIFO_DEQ] = 1;
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plic_priority[CDR_INT_RX0_FIFO_ENQ] = 1;
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plic_priority[CDR_INT_RX1_FIFO_ENQ] = 1;
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2025-01-16 16:34:48 +08:00
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*plic_threshold_0 = 0;
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2024-10-29 17:32:17 +08:00
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2024-11-05 17:48:34 +08:00
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2025-02-10 14:38:49 +08:00
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return 0;
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2024-10-29 17:32:17 +08:00
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}
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