Files
eb001/tb/sw/src/SlvMain.c

103 lines
2.0 KiB
C
Raw Normal View History

2024-10-29 17:32:17 +08:00
#include <stdint.h>
// #include "uart.h"
// #include "gpio.h"
// #include "timer.h"
2025-01-16 16:34:48 +08:00
#include "tl2cdr.h"
#include "system_cfg.h"
#include "halfLvdsMacSvr.h"
#include "sysDef.h"
2024-11-05 17:48:34 +08:00
#ifdef __riscv_i
#define USING_POLL_STRATEGY
#endif
volatile uint32_t *const plic_priority = (uint32_t *)(0xc000000U);
2025-01-15 15:44:29 +08:00
2025-01-16 16:34:48 +08:00
volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
2025-01-15 15:44:29 +08:00
2025-01-16 16:34:48 +08:00
volatile uint32_t *plic_threshold_0 = (uint32_t*)( 0xc000000U + 0X200000 );
volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
2025-01-15 15:44:29 +08:00
static void error();
static uint32_t init_plic(void);
2025-01-15 15:44:29 +08:00
void main()
{
init_plic();
2025-01-15 15:44:29 +08:00
//复位脉冲
*tx0_softReset = 1;
*tx1_softReset = 1;
*rx0_softReset = 1;
*rx1_softReset = 1;
2025-01-15 15:44:29 +08:00
2025-01-16 16:34:48 +08:00
//tx0 下行
//tx1 上行
//rx0 下行
//rx1 上行
#ifdef USING_POLL_STRATEGY
//使用查询策略 POLL_STRATEGY 操作 half lvds mac
HLM_poll(WORKMODE_SLAVE);
2025-01-15 15:44:29 +08:00
#else
//使用中断策略操作half lvds mac
HLM_work_with_isr(WORKMODE_SLAVE);
#endif
while (1);
}
void error() {
while(1);
}
uint32_t init_plic(void)
{
/*初始化plic*/
*plic_enable_0_31 = 1 << CDR_INT_TX0END
| 1 << CDR_INT_TX1END
| 1 << CDR_INT_RX0ERROR
| 1 << CDR_INT_RX1ERROR
| 1 << CDR_INT_RX0START
| 1 << CDR_INT_RX1START
| 1 << CDR_INT_RX0END
| 1 << CDR_INT_RX1END
//| 1 << CDR_INT_TX0_FIFO_DEQ
//| 1 << CDR_INT_TX1_FIFO_DEQ
| 1 << CDR_INT_RX0_FIFO_ENQ
| 1 << CDR_INT_RX1_FIFO_ENQ
;
plic_priority[CDR_INT_TX0END] = 1;
plic_priority[CDR_INT_TX1END] = 1;
plic_priority[CDR_INT_RX0ERROR] = 1;
plic_priority[CDR_INT_RX1ERROR] = 1;
plic_priority[CDR_INT_RX0START] = 1;
plic_priority[CDR_INT_RX1START] = 1;
plic_priority[CDR_INT_RX0END] = 1;
plic_priority[CDR_INT_RX1END] = 1;
plic_priority[CDR_INT_TX0_FIFO_DEQ] = 1;
plic_priority[CDR_INT_TX1_FIFO_DEQ] = 1;
plic_priority[CDR_INT_RX0_FIFO_ENQ] = 1;
plic_priority[CDR_INT_RX1_FIFO_ENQ] = 1;
2025-01-16 16:34:48 +08:00
*plic_threshold_0 = 0;
2024-10-29 17:32:17 +08:00
2024-11-05 17:48:34 +08:00
return 0;
2024-10-29 17:32:17 +08:00
}