eb001/src/main/scala/backBoard/shin/ShinTop.scala

package BACK

import chisel3._
import chisel3.util._


class ShinTopIO extends Bundle{
  val clk8x = Input(Bool())

  val dDatIn   = Input(Bool())
  val dDatOut  = Output(Bool())
  val uDatIn   = Input(Bool())
  val uDatOut  = Output(Bool())

  // val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  // val downOut = Decoupled(new AXIS_Bundle(8))

  // val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  // val upOut = Decoupled(new AXIS_Bundle(8))

	// val qspi = 
	// val interrupt = Output(Bool())
	// val ctrl      = Input(UInt(4.W))




  val iqspi = new QSPIInterfaceIO
  val ospi = new SSPIInterfaceIO
  val oqspi = new QSPIInterfaceIO


  // val req = Flipped(Valid(new Bundle{
  //   val txAddr    = UInt(15.W)
  //   val rxAddr    = UInt(15.W)
  //   val length  = UInt(12.W)
  // }))

  val rsp = Valid(new Bundle{
    val isError = Bool()
    // val length  = UInt(12.W)
  })

  val iSync = Output(Vec(4, Bool()))
  val oSync = Output(Vec(4, Bool()))

  val isSoftReset = Output(Bool())
  val ledTest = Output(UInt(8.W))

  val interrupt = Output(Bool())
}






abstract class ShinTopBase extends Module{
  val io: ShinTopIO = IO(new ShinTopIO)

  // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }



	val slaveParser  = Module(new SlaveParser )
	val masterParser = Module(new MasterParser)

  val downCDRIn  = Module(new CDRIn)
  val upCDRIn    = Module(new CDRIn)
  val downCDROut = Module(new CDROut)
  val upCDROut   = Module(new CDROut)

  val interface = Module(new Interface)

  io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U )
  
  io.isSoftReset := interface.io.isSoftReset
  io.interrupt   := interface.io.interrupt

  downCDRIn.io.serDat  := io.dDatIn
  downCDRIn.io.overCLK := io.clk8x
  downCDRIn.io.initEncryptor := interface.io.initEncryptor

  upCDRIn.io.serDat  := io.uDatIn
  upCDRIn.io.overCLK := io.clk8x
  upCDRIn.io.initEncryptor := interface.io.initEncryptor

  io.dDatOut := downCDROut.io.serDat
  io.uDatOut := upCDROut.io.serDat

  downCDROut.io.initEncryptor := interface.io.initEncryptor
  upCDROut.io.initEncryptor   := interface.io.initEncryptor

  //override
  when( slaveParser.io.isLoop & interface.io.cReg.modeSel === false.B){
    upCDRIn.io.serDat := downCDROut.io.serDat
    io.dDatOut := false.B
  }

  io.ospi  <> interface.io.ospi
  io.iqspi <> interface.io.iqspi
  io.oqspi <> interface.io.oqspi

  io.iSync := interface.io.sync
  io.oSync := interface.io.sync

  val sram = Seq(
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
  )


  val smUnit = Seq(
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
  )


  smUnit(0).io.sram_r <> interface.io.sram_r(0)
  smUnit(2).io.sram_r <> interface.io.sram_r(1)
  smUnit(4).io.sram_r <> interface.io.sram_r(2)
  smUnit(6).io.sram_r <> interface.io.sram_r(3)

  smUnit(1).io.sram_w := interface.io.sram_w(0)
  smUnit(3).io.sram_w := interface.io.sram_w(1)
  smUnit(5).io.sram_w := interface.io.sram_w(2)
  smUnit(7).io.sram_w := interface.io.sram_w(3)

  smUnit(0).io.deq := interface.io.dSMdeq(0)
  smUnit(2).io.deq := interface.io.dSMdeq(1)
  smUnit(4).io.deq := interface.io.dSMdeq(2)
  smUnit(6).io.deq := interface.io.dSMdeq(3)


  smUnit(1).io.enq := interface.io.uSMenq(0)
  smUnit(3).io.enq := interface.io.uSMenq(1)
  smUnit(5).io.enq := interface.io.uSMenq(2)
  smUnit(7).io.enq := interface.io.uSMenq(3)




  for( i <- 0 until 4 ){
    for( j <- 0 until 4 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }
  }

  for( i <- 4 until 8 ){
    for( j <- 0 until 2 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }    
  }




  //default
  {
    smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)

    smUnit(1).io.sram_r.enr := false.B
    smUnit(3).io.sram_r.enr := false.B
    smUnit(5).io.sram_r.enr := false.B
    smUnit(7).io.sram_r.enr := false.B
    smUnit(1).io.sram_r.addrr := 0.U
    smUnit(3).io.sram_r.addrr := 0.U
    smUnit(5).io.sram_r.addrr := 0.U
    smUnit(7).io.sram_r.addrr := 0.U

    slaveParser.io.sram_r(0).datar := 0.U
    slaveParser.io.sram_r(1).datar := 0.U
    slaveParser.io.sram_r(2).datar := 0.U
    slaveParser.io.sram_r(3).datar := 0.U
    masterParser.io.sram_r.datar := 0.U

    smUnit(0).io.enq := false.B
    smUnit(2).io.enq := false.B
    smUnit(4).io.enq := false.B
    smUnit(6).io.enq := false.B

    smUnit(1).io.deq := false.B
    smUnit(3).io.deq := false.B
    smUnit(5).io.deq := false.B
    smUnit(7).io.deq := false.B


    downCDRIn.io.axis.ready := false.B
    slaveParser.io.downIn.valid := false.B
    slaveParser.io.downIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.downOut.ready := false.B
    masterParser.io.downOut.ready := false.B
    downCDROut.io.axis.valid := false.B
    downCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    upCDRIn.io.axis.ready := false.B
    slaveParser.io.upIn.valid := false.B
    slaveParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
    masterParser.io.upIn.valid := false.B
    masterParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.upOut.ready := false.B
    upCDROut.io.axis.valid := false.B
    upCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    interface.io.mstDeltaTime := 0.U

    interface.io.slvDeltaTime := 0.U
    interface.io.deltaFinal   := 0.U

    interface.io.intMstTrig(0) := false.B
    interface.io.intMstTrig(1) := false.B

    interface.io.intSlvTrig(0) := false.B
    interface.io.intSlvTrig(1) := false.B
    interface.io.intSlvTrig(2) := false.B
    interface.io.intSlvTrig(3) := false.B
    interface.io.intSlvTrig(4) := false.B
    interface.io.intSlvTrig(5) := false.B
    interface.io.intSlvTrig(6) := false.B
    interface.io.intSlvTrig(7) := false.B

    interface.io.intHWTrig(0) := false.B
    interface.io.intHWTrig(1) := false.B

  }

}



trait ShinTopMaster{ this: ShinTopBase =>

  when( interface.io.cReg.modeSel === true.B ){
    masterParser.io.downOut <> downCDROut.io.axis
    masterParser.io.upIn    <> upCDRIn.io.axis
  }

  when( interface.io.cReg.modeSel === true.B ){

    when( interface.io.txReq.bits.rxSM === 0.U ){
      smUnit(0).io.sram_w := masterParser.io.sram_w
      smUnit(0).io.enq    := masterParser.io.rxEnq
    } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
      smUnit(2).io.sram_w := masterParser.io.sram_w
      smUnit(2).io.enq    := masterParser.io.rxEnq
    } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
      smUnit(4).io.sram_w := masterParser.io.sram_w
      smUnit(4).io.enq    := masterParser.io.rxEnq
    } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
      smUnit(6).io.sram_w := masterParser.io.sram_w
      smUnit(6).io.enq    := masterParser.io.rxEnq
    }

    when( interface.io.txReq.bits.txSM === 0.U ){
      smUnit(1).io.sram_r <> masterParser.io.sram_r
      smUnit(1).io.deq    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
      smUnit(3).io.sram_r <> masterParser.io.sram_r
      smUnit(3).io.deq    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
      smUnit(5).io.sram_r <> masterParser.io.sram_r
      smUnit(5).io.deq    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
      smUnit(7).io.sram_r <> masterParser.io.sram_r
      smUnit(7).io.deq    := masterParser.io.txDeq
    }



    interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
    interface.io.intMstTrig(0) := masterParser.io.txDeq
    interface.io.intMstTrig(1) := masterParser.io.rxEnq

  }

  masterParser.io.req         := interface.io.txReq.valid
  // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength

  io.rsp := masterParser.io.rsp

  masterParser.io.cReg := interface.io.cReg
  masterParser.io.mReg := interface.io.mReg

  
}


trait ShinTopSlave{ this: ShinTopBase =>

  when( interface.io.cReg.modeSel === false.B ){
    slaveParser.io.downIn  <> downCDRIn.io.axis
    downCDROut.io.axis <> slaveParser.io.downOut
    slaveParser.io.upIn    <> upCDRIn.io.axis
    upCDROut.io.axis <> slaveParser.io.upOut
  }

  slaveParser.io.cReg := interface.io.cReg
  slaveParser.io.sReg := interface.io.sReg


  when( interface.io.cReg.modeSel === false.B ){
    smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
    smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
    smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
    smUnit(6).io.sram_w := slaveParser.io.sram_w(3)

    smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
    smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
    smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
    smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)

    smUnit(0).io.enq := slaveParser.io.dSMenq(0)
    smUnit(2).io.enq := slaveParser.io.dSMenq(1)
    smUnit(4).io.enq := slaveParser.io.dSMenq(2)
    smUnit(6).io.enq := slaveParser.io.dSMenq(3)

    smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
    smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
    smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
    smUnit(7).io.deq := slaveParser.io.uSMdeq(3)

    interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
    interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime
    interface.io.deltaFinal   := slaveParser.io.deltaFinal

    interface.io.intSlvTrig(0) := slaveParser.io.dSMenq(0)
    interface.io.intSlvTrig(1) := slaveParser.io.uSMdeq(0)
    interface.io.intSlvTrig(2) := slaveParser.io.dSMenq(1)
    interface.io.intSlvTrig(3) := slaveParser.io.uSMdeq(1)
    interface.io.intSlvTrig(4) := slaveParser.io.dSMenq(2)
    interface.io.intSlvTrig(5) := slaveParser.io.uSMdeq(2)
    interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3)
    interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3)

    interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0)
    interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1)

  }

  slaveParser.io.intHWClr(0) := interface.io.intHWClr(0)
  slaveParser.io.intHWClr(1) := interface.io.intHWClr(1)

  interface.io.lvds <> slaveParser.io.lvds

  interface.io.localDevIndex := slaveParser.io.localDevIndex

  //从站链路寄存器
  // interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft
  // interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify
  // interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev
  interface.io.isDevOnRight := slaveParser.io.isDevOnRight
  interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
  interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
}


trait ShinTopWatchDog{ this: ShinTopBase =>


  val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
  val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }

  for( i <- 0 until 8 ){
    when( smUnit(i).io.enq ){
      isWdtSMEnable(2*i) := false.B
    } .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(i+1) ){
      isWdtSMEnable(2*i) := true.B
    }

    when( smUnit(i).io.deq ){
      isWdtSMEnable(2*i + 1) := false.B
    } .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(i+1) ){
      isWdtSMEnable(2*i + 1) := true.B
    }
  }

  for( i <- 0 until 16 ){
    when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){
      wdtSMCnt(i) := wdtSMCnt(i) + 1.U
    } .elsewhen( ~isWdtSMEnable(i) ){
      wdtSMCnt(i) := 0.U
    }

    // assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), s"Assert Failed! wdtSMCnt($i) is larger than wdtTarCnt, Special situation?" )
    
    interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1)
  }


  val isWdtRecEnable = RegInit(false.B)
  val wdtRecCnt = Reg(UInt(32.W))

  when( upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast ){
    isWdtRecEnable := false.B
  } .elsewhen( ~isWdtRecEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
    isWdtRecEnable := true.B
  }

  when( isWdtRecEnable & (wdtRecCnt < interface.io.cReg.wdtTarCnt(0)) ){
    wdtRecCnt := wdtRecCnt + 1.U
  } .elsewhen( ~isWdtRecEnable ){
    wdtRecCnt := 0.U
  }

  // assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" )

  interface.io.wdtTrigger(0) := wdtRecCnt === interface.io.cReg.wdtTarCnt(0)



}



class ShinTop extends ShinTopBase
with ShinTopMaster
with ShinTopSlave
with ShinTopWatchDog