eb001/src/main/scala/backBoard/shin/ShinTop.scala

package BACK

import chisel3._
import chisel3.util._


class ShinTopIO extends Bundle{
  val clk8x = Input(Bool())

  val dDatIn   = Input(Bool())
  val dDatOut  = Output(Bool())
  val uDatIn   = Input(Bool())
  val uDatOut  = Output(Bool())

  // val downIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  // val downOut = Decoupled(new AXIS_Bundle(8))

  // val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
  // val upOut = Decoupled(new AXIS_Bundle(8))

	// val qspi = 
	// val interrupt = Output(Bool())
	// val ctrl      = Input(UInt(4.W))

  val timeStamp = Input(UInt(64.W))

  val modeSel = Input(Bool())




  val req = Flipped(Valid(new Bundle{
    val txAddr    = UInt(15.W)
    val rxAddr    = UInt(15.W)
    val length  = UInt(12.W)
  }))
  val rsp = Valid(new Bundle{
    val isError = Bool()
    val length  = UInt(12.W)
  })
}



abstract class ShinTopBase extends Module{
  val io: ShinTopIO = IO(new ShinTopIO)

  // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }

	val slaveParser  = Module(new SlaveParser )
	val masterParser = Module(new MasterParser)

  val downCDRIn  = Module(new CDRIn)
  val upCDRIn    = Module(new CDRIn)
  val downCDROut = Module(new CDROut)
  val upCDROut   = Module(new CDROut)

  val interface = Module(new Interface)

  downCDRIn.io.serDat  := io.dDatIn
  downCDRIn.io.overCLK := io.clk8x

  upCDRIn.io.serDat  := io.uDatIn
  upCDRIn.io.overCLK := io.clk8x

  io.dDatOut := downCDROut.io.serDat
  io.uDatOut := upCDROut.io.serDat

  //override
  when( slaveParser.io.isLoop & io.modeSel === false.B){
    upCDRIn.io.serDat := downCDROut.io.serDat
    io.dDatOut := false.B
  }




  val sram = Seq(
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
    for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
  )


  val smUnit = Seq(
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 4) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
    Module( new SMUnit(depth = 2) ),
  )


  smUnit(0).io.sram_r <> interface.io.sram_r(0)
  smUnit(2).io.sram_r <> interface.io.sram_r(1)
  smUnit(4).io.sram_r <> interface.io.sram_r(2)
  smUnit(6).io.sram_r <> interface.io.sram_r(3)

  smUnit(1).io.sram_w := interface.io.sram_w(0)
  smUnit(3).io.sram_w := interface.io.sram_w(1)
  smUnit(5).io.sram_w := interface.io.sram_w(2)
  smUnit(7).io.sram_w := interface.io.sram_w(3)

  smUnit(0).io.deq := interface.io.dSMdeq(0)
  smUnit(2).io.deq := interface.io.dSMdeq(1)
  smUnit(4).io.deq := interface.io.dSMdeq(2)
  smUnit(6).io.deq := interface.io.dSMdeq(3)


  smUnit(1).io.enq := interface.io.uSMenq(0)
  smUnit(3).io.enq := interface.io.uSMenq(1)
  smUnit(5).io.enq := interface.io.uSMenq(2)
  smUnit(7).io.enq := interface.io.uSMenq(3)




  for( i <- 0 until 4 ){
    for( j <- 0 until 4 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }
  }

  for( i <- 4 until 8 ){
    for( j <- 0 until 2 ){
      sram(i)(j).io.clockr := clock.asBool
      sram(i)(j).io.clockw := clock.asBool

      smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
      sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
      sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
      sram(i)(j).io.enw   := smUnit(i).io.sram(j).wr.enw
      sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
      sram(i)(j).io.enr   := smUnit(i).io.sram(j).rd.enr
    }    
  }




  //default
  {
    smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
    smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)

    smUnit(1).io.sram_r.enr := false.B
    smUnit(3).io.sram_r.enr := false.B
    smUnit(5).io.sram_r.enr := false.B
    smUnit(7).io.sram_r.enr := false.B
    smUnit(1).io.sram_r.addrr := 0.U
    smUnit(3).io.sram_r.addrr := 0.U
    smUnit(5).io.sram_r.addrr := 0.U
    smUnit(7).io.sram_r.addrr := 0.U

    slaveParser.io.sram_r(0).datar := 0.U
    slaveParser.io.sram_r(1).datar := 0.U
    slaveParser.io.sram_r(2).datar := 0.U
    slaveParser.io.sram_r(3).datar := 0.U
    masterParser.io.sram_r.datar := 0.U

    smUnit(0).io.enq := false.B
    smUnit(2).io.enq := false.B
    smUnit(4).io.enq := false.B
    smUnit(6).io.enq := false.B

    smUnit(1).io.deq := false.B
    smUnit(3).io.deq := false.B
    smUnit(5).io.deq := false.B
    smUnit(7).io.deq := false.B


    downCDRIn.io.axis.ready := false.B
    slaveParser.io.downIn.valid := false.B
    slaveParser.io.downIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.downOut.ready := false.B
    masterParser.io.downOut.ready := false.B
    downCDROut.io.axis.valid := false.B
    downCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    upCDRIn.io.axis.ready := false.B
    slaveParser.io.upIn.valid := false.B
    slaveParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
    masterParser.io.upIn.valid := false.B
    masterParser.io.upIn.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))

    slaveParser.io.upOut.ready := false.B
    upCDROut.io.axis.valid := false.B
    upCDROut.io.axis.bits  := 0.U.asTypeOf(new AXIS_Bundle(8))
  }


}



trait ShinTopMaster{ this: ShinTopBase =>

  when(io.modeSel === true.B ){
    masterParser.io.downOut <> downCDROut.io.axis
    masterParser.io.upIn    <> upCDRIn.io.axis
  }

  when( io.modeSel === true.B ){

    when( interface.io.txReq.bits.rxSM === 0.U ){
      smUnit(0).io.sram_w := masterParser.io.sram_w
      smUnit(0).io.enq    := masterParser.io.rxEnq
    } .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
      smUnit(2).io.sram_w := masterParser.io.sram_w
      smUnit(2).io.enq    := masterParser.io.rxEnq
    } .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
      smUnit(4).io.sram_w := masterParser.io.sram_w
      smUnit(4).io.enq    := masterParser.io.rxEnq
    } .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
      smUnit(6).io.sram_w := masterParser.io.sram_w
      smUnit(6).io.enq    := masterParser.io.rxEnq
    }

    when( interface.io.txReq.bits.txSM === 0.U ){
      smUnit(1).io.sram_r <> masterParser.io.sram_r
      smUnit(1).io.deq    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
      smUnit(3).io.sram_r <> masterParser.io.sram_r
      smUnit(3).io.deq    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
      smUnit(5).io.sram_r <> masterParser.io.sram_r
      smUnit(5).io.deq    := masterParser.io.txDeq
    } .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
      smUnit(7).io.sram_r <> masterParser.io.sram_r
      smUnit(7).io.deq    := masterParser.io.txDeq
    }

    // _ := interface.io.smEnqAddr(0)
    // _ := interface.io.smDeqAddr(1)
    // _ := interface.io.smEnqAddr(2)
    // _ := interface.io.smDeqAddr(3)
    // _ := interface.io.smEnqAddr(4)
    // _ := interface.io.smDeqAddr(5)
    // _ := interface.io.smEnqAddr(6)
    // _ := interface.io.smDeqAddr(7)



  }

  masterParser.io.req := io.req
  io.rsp := masterParser.io.rsp

  // masterParser.io.trigAddr(0) := "hff".U
  // masterParser.io.trigAddr(1) := "hff".U

  masterParser.io.timeStamp := io.timeStamp
}


trait ShinTopSlave{ this: ShinTopBase =>

  when( io.modeSel === false.B ){
    slaveParser.io.downIn  <> downCDRIn.io.axis
    downCDROut.io.axis <> slaveParser.io.downOut
    slaveParser.io.upIn    <> upCDRIn.io.axis
    upCDROut.io.axis <> slaveParser.io.upOut
  }

  slaveParser.io.timeStamp := io.timeStamp

  val smEnqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）
  val smDeqAddr = Vec(8, UInt(16.W)) //触发SM切换缓冲区的地址 （或读或写）

  slaveParser.io.trigAddr(0) := interface.io.smEnqAddr(0)
  slaveParser.io.trigAddr(1) := interface.io.smDeqAddr(1)
  slaveParser.io.trigAddr(2) := interface.io.smEnqAddr(2)
  slaveParser.io.trigAddr(3) := interface.io.smDeqAddr(3)
  slaveParser.io.trigAddr(4) := interface.io.smEnqAddr(4)
  slaveParser.io.trigAddr(5) := interface.io.smDeqAddr(5)
  slaveParser.io.trigAddr(6) := interface.io.smEnqAddr(6)
  slaveParser.io.trigAddr(7) := interface.io.smDeqAddr(7)





  when( io.modeSel === false.B ){
    smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
    smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
    smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
    smUnit(6).io.sram_w := slaveParser.io.sram_w(3)

    smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
    smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
    smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
    smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)

    smUnit(0).io.enq := slaveParser.io.dSMenq(0)
    smUnit(2).io.enq := slaveParser.io.dSMenq(1)
    smUnit(4).io.enq := slaveParser.io.dSMenq(2)
    smUnit(6).io.enq := slaveParser.io.dSMenq(3)

    smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
    smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
    smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
    smUnit(7).io.deq := slaveParser.io.uSMdeq(3)    
  }



}






class ShinTop extends ShinTopBase
with ShinTopMaster
with ShinTopSlave