63 lines
1.1 KiB
Verilog
63 lines
1.1 KiB
Verilog
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/*
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Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`timescale 1 ns / 1 ps
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module gen_dffren # (
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parameter DW = 32,
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parameter rstValue = {DW{1'b0}}
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)
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(
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input en,
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input CLK,
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input RSTn
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);
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wire [DW-1:0] dffren_dnxt;
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wire [DW-1:0] dffren_qout;
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gen_dffr # ( .DW(DW), .rstValue(rstValue) ) dffren
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(
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.dnxt(dffren_dnxt),
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.qout(dffren_qout),
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.CLK(CLK),
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.RSTn(RSTn)
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);
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assign dffren_dnxt = en ? dnxt : dffren_qout;
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assign qout = dffren_qout;
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endmodule
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