58 lines
1020 B
Verilog
58 lines
1020 B
Verilog
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/*
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Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`timescale 1 ns / 1 ps
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module gen_dffr # (
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parameter DW = 32,
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parameter rstValue = {DW{1'b0}}
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)
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(
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input [DW-1:0] dnxt,
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output [DW-1:0] qout,
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input CLK,
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input RSTn
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);
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reg [DW-1:0] qout_r;
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always @(posedge CLK or negedge RSTn) begin
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if ( ~RSTn )
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qout_r <= #1 rstValue;
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else
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qout_r <= #1 dnxt;
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end
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assign qout = qout_r;
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endmodule
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