RuigeLee 46882b6b4d 缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口

2024-10-31 17:38:12 +08:00

..

Axis8toN.scala.bk

新主站发送逻辑

2024-10-09 17:37:15 +08:00

AxisNto8.scala.bk

新主站发送逻辑

2024-10-09 17:37:15 +08:00

BackBoardMst.scala.bk

Revert "重开ebus项目"

2024-09-10 16:36:30 +08:00

BackBoardSlv.scala.bk

Revert "重开ebus项目"

2024-09-10 16:36:30 +08:00

CDR4MultiIn.scala.bk

Revert "重开ebus项目"

2024-09-10 16:36:30 +08:00

CDRIn.scala

缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口

2024-10-31 17:38:12 +08:00

CDROut.scala

缩减后面积已经满足要求，时序违例，主要集中在alu和访存接口

2024-10-31 17:38:12 +08:00

CDROutBus.scala.bk

Revert "重开ebus项目"

2024-09-10 16:36:30 +08:00

crc32.scala

仿真，状态机错误

2024-09-10 18:39:35 +08:00

FSMC.scala.bk

Revert "重开ebus项目"

2024-09-10 16:36:30 +08:00

SpiSlv.scala.bk

Revert "重开ebus项目"

2024-09-10 16:36:30 +08:00