154 lines
4.7 KiB
Scala
154 lines
4.7 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
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val sck = Wire(Bool())
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val mosi = Wire(Bool())
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val csn = Wire(Bool())
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val clk100M = Wire(Bool())
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val spiRegDown = Module(new SpiSRAMDown)
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val spiRegUp = Module(new SpiSRAMUp)
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spiRegDown.io.clockr := clk100M
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spiRegDown.io.clockw := clock.asBool
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spiRegUp.io.clockr := clock.asBool
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spiRegUp.io.clockw := clk100M
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val localUpdate = RegInit(0.U(16.W))
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val shiftSCK = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
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val shiftCSn = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
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val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
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val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
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val isSckPosedgeNext = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(isSckPosedge, 2, false.B, true.B) }
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val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
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val exMask_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(16.W)) }
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val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
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val pageSel = cmd_100M(5,4)
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val spiCmd = cmd_100M(3,0)
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val bitSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(3.W)) }
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val byteSel = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(5.W)) }
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spiRegDown.io.addrr := Cat(pageSel, byteSel)
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spiRegDown.io.enr := spiCmd === 0.U & isSckPosedgeNext(0)
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spiRegUp.io.addrw := Cat(pageSel, byteSel - 1.U)
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spiRegUp.io.dataw := withClockAndReset( clk100M.asClock, reset ){ RegEnable(exReg_100M, bitSel === 0.U) }
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spiRegUp.io.enw := isSckPosedgeNext(1) & ~shiftCSn(1+1) & bitSel === 0.U & spiCmd === 1.U
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withClockAndReset( clk100M.asClock, reset ){//100M
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when( shiftCSn(2) & ~shiftCSn(1) ){
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bitSel := 0.U
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byteSel := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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bitSel := bitSel + 1.U
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when( bitSel === 7.U ){
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byteSel := byteSel + 1.U
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}
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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bitSel := 0.U
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byteSel := 0.U
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cmd_100M := 0.U
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} .elsewhen( isSckPosedge & ~shiftCSn(1) & byteSel === 0.U ){ //CS为低，且SCK上跳的第0byte
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cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
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}
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when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
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exReg_100M := upReg(0)
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} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
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when( byteSel === 1.U ){
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exReg_100M := upReg(1)
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} .elsewhen( spiCmd === 2.U & byteSel === 2.U ){
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exReg_100M := localUpdate(7,0)
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} .elsewhen( spiCmd === 2.U & byteSel === 3.U ){
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exReg_100M := localUpdate(15,8)
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} .elsewhen( spiCmd === 0.U & (byteSel =/= 0.U | byteSel =/= 1.U) ){
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exReg_100M := spiRegDown.io.datar
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}
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} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
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exReg_100M := Cat( exReg_100M(6 ,0), shiftMOSI(1) )
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}
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when( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U & spiCmd === 3.U ){
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exMask_100M := Cat( exReg_100M, exMask_100M(7,0) )
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} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(1) & byteSel === 4.U & bitSel === 0.U & spiCmd === 3.U ){
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exMask_100M := Cat( exMask_100M(15,8), exReg_100M )
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}
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}
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}
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class SpiSlv extends BackBoardSlvLocal
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with BackBoardSlvStatusPR
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with BackBoardSpiSlv{
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val spi = IO(new Bundle{
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val sck = Input(Bool())
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val mosi = Input(Bool())
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val miso = Output(Bool())
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val csn = Input(Bool())
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})
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val clk100MIO = IO(Input(Bool()))
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val interrupt = IO(Output(Bool()))
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sck := spi.sck
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mosi := spi.mosi
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csn := spi.csn
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spi.miso := exReg_100M.extract(exReg_100M.getWidth-1)
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clk100M := clk100MIO
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val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)
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when( isCrcPass ){
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localUpdate := localUpdate & ~( 1.U << downRegTemp(0)(3,0) )
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} .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) ){
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localUpdate := localUpdate & ~exMask_100M
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}
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spiRegDown.io.enw := io.lvdsSlv.downstream_rx_data_valid & (downCnt =/= 0.U | downCnt =/= 1.U)
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spiRegDown.io.dataw := io.lvdsSlv.downstream_rx_data_out
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spiRegDown.io.addrw := Cat( downRegTemp(0)(3,0), downCnt(4,0))
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spiRegUp.io.enr := io.lvdsSlv.upstream_tx_data_ready
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spiRegUp.io.addrr := Cat( statusPage, upCnt(4,0)+1.U )
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io.lvdsSlv.upstream_tx_data_in :=
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Mux(upCnt === 0.U | upCnt === 1.U | statusPage === 15.U, upReg(upCnt), spiRegUp.io.datar)
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val int = RegInit(false.B); interrupt := int
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when( int ){
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int := false.B
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} .elsewhen( RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & ~io.lvdsSlv.upstream_tx_data_ready ){
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int := true.B
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}
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}
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