532 lines
10 KiB
Verilog
532 lines
10 KiB
Verilog
`timescale 1 ns / 1 ps
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module ShinTopSpiTb(
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);
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reg clock;
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reg reset;
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reg clk8x;
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wire [3:0] dDat_w;
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wire [3:0] uDat_w;
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reg [4:0] spi_sck;
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reg [4:0] spi_mosi;
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wire [4:0] spi_miso;
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reg [4:0] spi_csn;
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ShinTop s_ShinTop_Mst(
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.clock(clock),
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.reset(reset),
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.io_clk8x(clk8x),
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.io_dDatIn(1'b0),
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.io_dDatOut(dDat_w[0]),
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.io_uDatIn(uDat_w[0]),
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.io_uDatOut(),
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.io_ospi_sck (spi_sck[0]),
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.io_ospi_mosi(spi_mosi[0]),
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.io_ospi_miso(spi_miso[0]),
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.io_ospi_csn (spi_csn[0]),
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.io_rsp_valid(),
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.io_rsp_bits_isError(),
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.io_rsp_bits_length()
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);
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ShinTop s_ShinTop_slv0(
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.clock(clock),
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.reset(reset),
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.io_clk8x(clk8x),
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.io_dDatIn(dDat_w[0]),
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.io_dDatOut(dDat_w[1]),
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.io_uDatIn(uDat_w[1]),
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.io_uDatOut(uDat_w[0]),
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.io_ospi_sck (spi_sck[1]),
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.io_ospi_mosi(spi_mosi[1]),
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.io_ospi_miso(spi_miso[1]),
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.io_ospi_csn (spi_csn[1]),
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.io_rsp_valid(),
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.io_rsp_bits_isError(),
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.io_rsp_bits_length()
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);
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ShinTop s_ShinTop_slv1(
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.clock(clock),
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.reset(reset),
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.io_clk8x(clk8x),
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.io_dDatIn(dDat_w[1]),
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.io_dDatOut(dDat_w[2]),
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.io_uDatIn(uDat_w[2]),
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.io_uDatOut(uDat_w[1]),
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.io_ospi_sck (spi_sck[2]),
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.io_ospi_mosi(spi_mosi[2]),
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.io_ospi_miso(spi_miso[2]),
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.io_ospi_csn (spi_csn[2]),
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.io_rsp_valid(),
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.io_rsp_bits_isError(),
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.io_rsp_bits_length()
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);
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ShinTop s_ShinTop_slv2(
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.clock(clock),
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.reset(reset),
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.io_clk8x(clk8x),
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.io_dDatIn(dDat_w[2]),
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.io_dDatOut(dDat_w[3]),
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.io_uDatIn(uDat_w[3]),
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.io_uDatOut(uDat_w[2]),
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.io_ospi_sck (spi_sck[3]),
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.io_ospi_mosi(spi_mosi[3]),
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.io_ospi_miso(spi_miso[3]),
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.io_ospi_csn (spi_csn[3]),
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.io_rsp_valid(),
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.io_rsp_bits_isError(),
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.io_rsp_bits_length()
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);
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ShinTop s_ShinTop_slv3(
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.clock(clock),
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.reset(reset),
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.io_clk8x(clk8x),
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.io_dDatIn(dDat_w[3]),
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.io_dDatOut(),
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.io_uDatIn(1'b0),
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.io_uDatOut(uDat_w[3]),
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.io_ospi_sck (spi_sck[4]),
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.io_ospi_mosi(spi_mosi[4]),
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.io_ospi_miso(spi_miso[4]),
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.io_ospi_csn (spi_csn[4]),
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.io_rsp_valid(),
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.io_rsp_bits_isError(),
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.io_rsp_bits_length()
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);
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initial begin
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clock = 0;
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clk8x = 0;
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reset = 0;
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spi_sck = 5'b0;
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spi_mosi = 5'b0;
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spi_csn = 5'b11111;
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#100
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reset <= 1;
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#240
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reset <= 0;
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#3000000
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$display("Time Out !!!");
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$stop;
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end
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initial begin
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forever begin #10 clk8x <= ~clk8x; end
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end
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initial begin
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forever begin #80 clock <= ~clock; end
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end
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initial
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begin
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$dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称
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$dumpvars(0, ShinTopSpiTb);//tb模块名称
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end
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initial begin
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for( integer i = 0; i < 5; i = i + 1 ) begin
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forever begin
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#1000 spi_sck[i] <= spi_csn[i] == 1'b0 ? ~spi_sck[i] : 1'b0;
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end
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end
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end
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reg [7:0] txBuf[0:2047];
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reg [7:0] rxBuf[0:2047];
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task spi_trans( input [15:0] address, input [7:0] cmd, input [10:0] length, input [7:0] idx );
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reg [10:0] transCnt;
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reg [7:0] exChangeReg;
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begin
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#10
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spi_csn[idx] <= 1'b0;
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transCnt <= 0;
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exChangeReg <= address[7:0];
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repeat(8) begin
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@(posedge spi_sck[idx]) #5
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exChangeReg <= {exChangeReg[6:0], spi_miso[idx]};
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spi_mosi[idx] <= exChangeReg[7];
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end
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exChangeReg <= address[15:8];
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repeat(8) begin
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@(posedge spi_sck[idx]) #5
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exChangeReg <= {exChangeReg[6:0], spi_miso[idx]};
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spi_mosi[idx] <= exChangeReg[7];
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end
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exChangeReg <= cmd;
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repeat(8) begin
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@(posedge spi_sck[idx]) #5
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exChangeReg <= {exChangeReg[6:0], spi_miso[idx]};
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spi_mosi[idx] <= exChangeReg[7];
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end
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while( transCnt < length ) begin
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exChangeReg <= txBuf[transCnt];
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transCnt <= transCnt + 1;
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repeat(8) begin
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@(posedge spi_sck[idx]) #5
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exChangeReg <= {exChangeReg[6:0], spi_miso[idx]};
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spi_mosi[idx] <= exChangeReg[7];
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end
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rxBuf[transCnt] <= exChangeReg;
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end
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@(negedge spi_sck[idx]) #5
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spi_csn[idx] <= 1'b1;
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end
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endtask
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`define SPI_WRITE 8'h0
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`define SPI_READ 8'h1
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initial begin
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#1000
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//设置主站从站
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txBuf[0] = 8'h01;
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spi_trans( (16'h0), (`SPI_WRITE), (1), (0) );
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#1000
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txBuf[0] = 8'h02;
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spi_trans( (16'h0), (`SPI_WRITE), (1), (1) );
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#1000
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spi_trans( (16'h0), (`SPI_WRITE), (1), (2) );
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#1000
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spi_trans( (16'h0), (`SPI_WRITE), (1), (3) );
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#1000
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spi_trans( (16'h0), (`SPI_WRITE), (1), (4) );
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//嗅探
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#10000
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begin
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//设置SM1在写入0x3地址触发enq
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txBuf[0] = 8'h03;
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txBuf[1] = 8'h00;
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spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
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//无子报文
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txBuf[0] = 8'h00;
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txBuf[1] = 8'h01;//heeader length 0 嗅探包1
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txBuf[2] = 8'h00;
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txBuf[3] = 8'h00;
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spi_trans( (16'h1000), (`SPI_WRITE), (4), (0) ); //写入SM1
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//发布请求
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txBuf[0] = 8'h04;
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txBuf[1] = 8'h00;
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spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
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txBuf[0] = 8'h01;
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spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
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end
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// 顺序索引
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#50000
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#50000
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#50000
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begin
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//设置SM1在写入0xd地址触发enq
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txBuf[0] = 8'h0d;
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txBuf[1] = 8'h00;
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spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
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txBuf[0] = 8'h00;
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txBuf[1] = 8'ha0;//heeader length 10
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txBuf[2] = 8'h00;
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txBuf[3] = 8'h00;
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//子报文
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//设置顺序地址
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txBuf[4] = 8'h0; //设备索引
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txBuf[5] = 8'h0; //设备索引、类型
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txBuf[6] = $random; //地址
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txBuf[7] = $random; //地址
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txBuf[8] = 8'hd0; //命令d 负载长度2
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txBuf[9] = 8'd02; //负载长度2
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txBuf[10] = 8'h0; //工作计数0
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txBuf[11] = 8'h0; //工作计数0
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txBuf[12] = 8'h0; //负载
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txBuf[13] = 8'h0; //负载
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spi_trans( (16'h1000), (`SPI_WRITE), (14), (0) ); //写入SM1
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//发布请求
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txBuf[0] = 8'h0e;
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txBuf[1] = 8'h00;
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spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
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txBuf[0] = 8'h01;
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spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
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end
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//读写
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#50000
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#50000
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#50000
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#50000
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begin
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//设置SM1在写入516地址触发enq
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txBuf[0] = 8'h03;
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txBuf[1] = 8'h02;
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spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
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txBuf[0] = 8'h20;
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txBuf[1] = 8'h00;//heeader length 512
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txBuf[2] = 8'h00;
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txBuf[3] = 8'h00;
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//子报文
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txBuf[4] = 8'h0;
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txBuf[5] = 8'h8; //index = 2
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txBuf[6] = 8'h08; //地址 //SM0
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txBuf[7] = 8'h30; //地址 //偏置
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txBuf[8] = 8'h20; //命令2 长度56
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txBuf[9] = 8'd56; //长度
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txBuf[10] = $random;
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txBuf[11] = $random;
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for( integer j = 0; j < 64-8; j = j + 1 ) begin
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@(posedge clock) #3
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txBuf[12+j] = $random;
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end
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//-------------------------
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//子报文
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txBuf[68] = 8'h0;
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txBuf[69] = 8'h4; //index = 1
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txBuf[70] = 8'h08; //地址 //SM0
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txBuf[71] = 8'h40; //地址 //偏置
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txBuf[72] = 8'h10; //命令1 长度56
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txBuf[73] = 8'd56; //长度
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txBuf[74] = $random;
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txBuf[75] = $random;
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for( integer j = 0; j < 64-8; j = j + 1 ) begin
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@(posedge clock) #3
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txBuf[76+j] = $random;
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end
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//-------------------------
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//子报文
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txBuf[132] = 8'h0;
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txBuf[133] = 8'hc; //index = 3
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txBuf[134] = 8'h09; //地址 //SM1
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txBuf[135] = 8'h40; //地址 //偏置
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txBuf[136] = 8'h00; //命令0 长度56
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txBuf[137] = 8'd56; //长度
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txBuf[138] = $random;
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txBuf[139] = $random;
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for( integer j = 0; j < 64-8; j = j + 1 ) begin
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@(posedge clock) #3
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txBuf[140+j] = $random;
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end
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//-------------------------
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for( integer i = 0 ; i < 5; i = i + 1) begin
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//子报文
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txBuf[196+i*64+0] = $random;
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txBuf[196+i*64+1] = 8'h0; //index = random
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txBuf[196+i*64+2] = $random;
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txBuf[196+i*64+3] = $random;
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txBuf[196+i*64+4] = 8'h00; //命令0 长度56
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txBuf[196+i*64+5] = 8'd56; //长度
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txBuf[196+i*64+6] = $random;
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txBuf[196+i*64+7] = $random;
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for( integer j = 0; j < 64-8; j = j + 1 ) begin
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@(posedge clock) #3
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txBuf[196+i*64+8+j] = $random;
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end
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end
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spi_trans( (16'h1000), (`SPI_WRITE), (516), (0) ); //写入SM1
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//发布请求
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txBuf[0] = 8'h04;
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txBuf[1] = 8'h02;
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spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
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txBuf[0] = 8'h01;
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spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
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end
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// 同步
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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#90000
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begin
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//设置SM1在写入0x3地址触发enq
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txBuf[0] = 8'h17;
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txBuf[1] = 8'h00;
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spi_trans( (16'h0202), (`SPI_WRITE), (2), (0) );
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txBuf[0] = 8'h01;
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txBuf[1] = 8'h40;//heeader length 20
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txBuf[2] = 8'h00;
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txBuf[3] = 8'h00;
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//子报文
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//设置同步
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txBuf[4] = 8'h0; //设备索引
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txBuf[5] = 8'h0; //设备索引、类型
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txBuf[6] = $random; //地址
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txBuf[7] = $random; //地址
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txBuf[8] = 8'he0; //命令d 负载长度2
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txBuf[9] = 8'h0c; //负载长度c
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txBuf[10] = 8'h0; //工作计数0
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txBuf[11] = 8'h0; //工作计数0
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txBuf[12] = 0;//timeStamp[7:0]; //负载
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txBuf[13] = 0;//timeStamp[15:8]; //负载
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txBuf[14] = 0;//timeStamp[23:16]; //负载
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txBuf[15] = 0;//timeStamp[31:24]; //负载
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txBuf[16] = 0;//timeStamp[39:32]; //负载
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txBuf[17] = 0;//timeStamp[47:40]; //负载
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txBuf[18] = 0;//timeStamp[55:48]; //负载
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txBuf[19] = 0;//timeStamp[63:56]; //负载
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txBuf[20] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[ 7: 0]; //负载
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txBuf[21] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[15: 8]; //负载
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txBuf[22] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[23:16]; //负载
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txBuf[23] = 0;//s_ShinTop_Mst.masterParser.deltaTimeStamp[31:24]; //负载
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spi_trans( (16'h1000), (`SPI_WRITE), (24), (0) ); //写入SM1
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//发布请求
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txBuf[0] = 8'h18;
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txBuf[1] = 8'h00;
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spi_trans( (16'h21), (`SPI_WRITE), (2), (0) );//写入长度
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txBuf[0] = 8'h01;
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spi_trans( (16'h20), (`SPI_WRITE), (1), (0) );//发送SM0 接收SM0, 请求发送
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end
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end
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endmodule
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