121 lines
2.5 KiB
Scala
121 lines
2.5 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class Header_Info_Bundle extends Bundle{
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val operator = UInt(8.W)
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val length = UInt(8.W)
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val param = Vec(3, UInt(16.W))
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def init = operator === 0.U
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def sync = operator === 1.U
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def boardCast = operator === 2.U
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def uniCast = operator === 3.U
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}
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abstract class ShinMstPhyBase extends Module{
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val mirrorDown = Module(new MirrorSRAMDP())
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val mirrorUp = Module(new MirrorSRAMDP())
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val cdrOut = Module(new CDROut)
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}
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trait ShinMstSend{ this: ShinMstPhyBase =>
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def isSendTrig: Bool
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def isRecvEnd: Bool
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def isTimeout: Bool
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val sendStateNext = Wire( UInt(3.W) )
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val sendStateCurr = RegNext( sendStateNext, 0.U )
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val sendHeader = Wire( new Header_Info_Bundle )
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val sendCnt = Reg(UInt(10.W))
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sendStateNext := Mux1H(Seq(
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(sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
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(sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCnt === ((sendHeader.getWidth()/8)*2-1).U, 2.U, 1.U ),
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(sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCnt === (sendHeader.length << 1) - 1.U, 3.U, 2.U ),
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(sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
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))
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when( sendStateCurr === 0.U ){
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when( sendStateNext === 1.U ) {
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sendCnt := 0.U
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}
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} .elsewhen( sendStateCurr === 1.U ){
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when( cdrOut.io.axis.fire ){
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sendCnt := Mux( sendStateNext =/= 2.U, sendCnt + 1.U, 0.U )
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}
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} .elsewhen( sendStateCurr === 2.U ){
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when( cdrOut.io.axis.fire ){
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sendCnt := Mux( sendStateNext =/= 3.U, sendCnt + 1.U, 0.U )
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}
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}
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cdrOut.io.axis.valid := sendStateCurr === 1.U | sendStateCurr === 2.U
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cdrOut.io.axis.bits.tdata :=
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Mux1H(Seq(
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( sendStateCurr === 1.U ) -> sendHeader.asUInt >> (sendCnt << 3),
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( sendStateCurr === 2.U ) -> Mux( sendCnt.extract(0), mirrorDown(7,0), mirrorDown(15,8) ),
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))
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cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCnt === (sendHeader.length << 1) - 1.U
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cdrOut.io.axis.bits.tuser := false.B
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}
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trait ShinMstRecv{ this: ShinMstPhyBase =>
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}
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abstract class ShinMstLinkBase extends ShinMstPhyBase
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with ShinMstSend
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with ShinMstRecv
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trait ShinMstInit{ this: ShinMstLinkBase =>
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}
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trait ShinMstSync{ this: ShinMstLinkBase =>
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}
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trait ShinMstTrans{ this: ShinMstLinkBase =>
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}
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trait ShinMstError{ this: ShinMstLinkBase =>
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}
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trait ShinMstInterface{ this: ShinMstLinkBase =>
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}
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class ShinMst extends ShinMstLinkBase
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with ShinMstInit
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with ShinMstSync
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with ShinMstTrans
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with ShinMstError
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with ShinMstInterface
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