package BACK

import chisel3._
import chisel3.util._

class Header_Info_Bundle extends Bundle{
  val operator = UInt(8.W)
  val length   = UInt(8.W)
  val param    = Vec(3, UInt(16.W))

  def init = operator === 0.U
  def sync = operator === 1.U
  def boardCast = operator === 2.U
  def uniCast   = operator === 3.U
}



abstract class ShinMstPhyBase extends Module{

  val mirrorDown = Module(new MirrorSRAMDP())
  val mirrorUp   = Module(new MirrorSRAMDP())



  val cdrOut = Module(new CDROut)

}


trait ShinMstSend{ this: ShinMstPhyBase =>
  def isSendTrig: Bool
  def isRecvEnd: Bool
  def isTimeout: Bool


  val sendStateNext = Wire( UInt(3.W) )
  val sendStateCurr = RegNext( sendStateNext, 0.U )

  val sendHeader = Wire( new Header_Info_Bundle )

  val sendCnt = Reg(UInt(10.W))

  sendStateNext := Mux1H(Seq(
    (sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
    (sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCnt === ((sendHeader.getWidth()/8)*2-1).U, 2.U, 1.U ),
    (sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCnt === (sendHeader.length << 1) - 1.U,    3.U, 2.U ),
    (sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
  ))

  when( sendStateCurr === 0.U ){
    when( sendStateNext === 1.U ) {
      sendCnt := 0.U
    }
  } .elsewhen( sendStateCurr === 1.U ){
    when( cdrOut.io.axis.fire ){
      sendCnt := Mux( sendStateNext =/= 2.U, sendCnt + 1.U, 0.U )
    }
  } .elsewhen( sendStateCurr === 2.U ){
    when( cdrOut.io.axis.fire ){
      sendCnt := Mux( sendStateNext =/= 3.U, sendCnt + 1.U, 0.U )
    }
  }

  cdrOut.io.axis.valid := sendStateCurr === 1.U | sendStateCurr === 2.U
  cdrOut.io.axis.bits.tdata := 
    Mux1H(Seq(
      ( sendStateCurr === 1.U ) -> sendHeader.asUInt >> (sendCnt << 3),
      ( sendStateCurr === 2.U ) -> Mux( sendCnt.extract(0), mirrorDown(7,0), mirrorDown(15,8) ),
    ))
  cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCnt === (sendHeader.length << 1) - 1.U
  cdrOut.io.axis.bits.tuser := false.B



}

trait ShinMstRecv{ this: ShinMstPhyBase =>

}




abstract class ShinMstLinkBase extends ShinMstPhyBase
with ShinMstSend
with ShinMstRecv



trait ShinMstInit{ this: ShinMstLinkBase =>

}

trait ShinMstSync{ this: ShinMstLinkBase =>

}

trait ShinMstTrans{ this: ShinMstLinkBase =>

}

trait ShinMstError{ this: ShinMstLinkBase =>

}

trait ShinMstInterface{ this: ShinMstLinkBase =>

}




class ShinMst extends ShinMstLinkBase
with ShinMstInit
with ShinMstSync
with ShinMstTrans
with ShinMstError
with ShinMstInterface