41 lines
744 B
Plaintext
41 lines
744 B
Plaintext
package BACK
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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class FSMCMemIO extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
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val tld = new DecoupledIO(new TLBundleD(edge.bundle))
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}
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abstract class FSMCMemBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
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val io: FSMCMemIO = IO(new FSMCMemIO)
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val sram = Module(new )
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}
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trait FSMCMemFSMC{ this: FSMCMemBase =>
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}
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trait FSMCMemTileLink { this: FSMCMemBase =>
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}
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class FSMCMem(edge: TLEdgeIn)(implicit p: Parameters) extends FSMCMemBase(edge)
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with FSMCMemFSMC
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with FSMCMemTileLink
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{
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}
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