package BACK

import chisel3._
import chisel3.util._

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._




class FSMCMemIO extends Bundle{
  val FSMC = new FSMC_Port_Bundle

  val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
  val tld = new DecoupledIO(new TLBundleD(edge.bundle))
}

abstract class FSMCMemBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
  val io: FSMCMemIO = IO(new FSMCMemIO)

  val sram = Module(new )
}

trait FSMCMemFSMC{ this: FSMCMemBase =>


}

trait FSMCMemTileLink { this: FSMCMemBase =>

}

class FSMCMem(edge: TLEdgeIn)(implicit p: Parameters) extends FSMCMemBase(edge)
with FSMCMemFSMC
with FSMCMemTileLink
{

}