87 lines
2.1 KiB
Plaintext
87 lines
2.1 KiB
Plaintext
package BACK
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import chisel3._
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import chisel3.util._
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class BackPlaneChainTestIO extends Bundle{
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val clk400 = Input( Vec(6, Bool() ))
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val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle))
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val led = Output( Vec( 5, Bool() ) )
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}
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class BackPlaneChainTest extends Module{
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val io: BackPlaneChainTestIO = IO(new BackPlaneChainTestIO)
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val mst = Module(new BackBoardMst)
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val slv = for( i <- 0 until 5 ) yield { Module(new BackBoardSlv) }
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mst.io.clk4 := io.clk400(5)
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withClockAndReset( io.clk400(5).asClock, reset.asAsyncReset ){
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io.spi.ready := true.B
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val cnt = RegInit(0.U(7.W))
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val spiInfo = Reg( new CDR_Master_Interface_Bundle )
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mst.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
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val cs = RegInit(true.B); mst.io.CS := cs
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val sckCnt = RegInit(1.U(2.W)); mst.io.SCK := sckCnt.extract(1) === 1.U
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when( ~cs ){
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sckCnt := sckCnt + 1.U
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}
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when( io.spi.fire ){
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cs := false.B
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cnt := 0.U
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spiInfo := io.spi.bits
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} .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){
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cnt := cnt + 1.U
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spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), mst.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
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} .elsewhen( cnt === 63.U & sckCnt === "b11".U ){
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cs := true.B
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}
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}
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for( i <- 0 until 5 ) {
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slv(i).io.localHost := i.U
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slv(i).io.clk4 := io.clk400(i)
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slv(i).sw := 0.U
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slv(i).qeiA := false.B
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slv(i).qeiB := false.B
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io.led(i) := slv(i).led.extract(0).asBool
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}
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slv(0).io.upStreamReqDat := mst.io.downStreamRespdat
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mst.io.downStreamReqDat := slv(0).io.upStreamRespdat
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slv(1).io.upStreamReqDat := slv(0).io.downStreamRespdat
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slv(0).io.downStreamReqDat := slv(1).io.upStreamRespdat
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slv(2).io.upStreamReqDat := slv(1).io.downStreamRespdat
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slv(1).io.downStreamReqDat := slv(2).io.upStreamRespdat
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slv(3).io.upStreamReqDat := slv(2).io.downStreamRespdat
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slv(2).io.downStreamReqDat := slv(3).io.upStreamRespdat
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slv(4).io.upStreamReqDat := slv(3).io.downStreamRespdat
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slv(3).io.downStreamReqDat := slv(4).io.upStreamRespdat
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slv(4).io.downStreamReqDat := slv(4).io.downStreamRespdat
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} |