89 lines
1.3 KiB
Verilog
89 lines
1.3 KiB
Verilog
`timescale 1 ns / 1 ps
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module backSys_TB (
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);
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reg clock;
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reg reset;
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reg overCLK;
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wire io_uDatIn;
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wire io_uDatOut;
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wire io_dDatIn;
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wire io_dDatOut;
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BackSys s_BackSys(
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.clock(clock),
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.reset(reset),
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.io_overCLK(overCLK),
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.io_uDatIn(io_uDatIn),
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.io_uDatOut(io_uDatOut),
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.io_dDatIn(io_dDatIn),
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.io_dDatOut(io_dDatOut)
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);
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initial begin
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clock = 0;
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reset = 1;
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#200
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reset <= 0;
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#160000
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$display("Time Out !!!");
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$stop;
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end
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initial begin
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forever begin #40 clock <= ~clock; end
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end
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initial begin
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forever begin #10 overCLK <= ~overCLK; end
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end
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`define SRAM0 s_BackSys.sram.mem_0
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`define SRAM1 s_BackSys.sram.mem_1
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`define SRAM2 s_BackSys.sram.mem_2
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`define SRAM3 s_BackSys.sram.mem_3
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localparam DP = 2**14;
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integer i, by;
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reg [7:0] mem [0:200000];
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initial begin
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$readmemh("./tb/sw/build/test.verilog", mem);
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for ( i = 0; i < DP; i = i + 1 ) begin
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`SRAM0[i] = | mem[i*4+0] ? mem[i*4+0]: 8'h0;
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`SRAM1[i] = | mem[i*4+1] ? mem[i*4+1]: 8'h0;
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`SRAM2[i] = | mem[i*4+2] ? mem[i*4+2]: 8'h0;
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`SRAM3[i] = | mem[i*4+3] ? mem[i*4+3]: 8'h0;
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// $display("ITCM %h: %h,%h", i*4,`SRAM_ODD.ram[i],`SRAM_EVE.ram[i]);
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end
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end
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initial
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begin
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$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
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$dumpvars(0, backSys_TB);//tb模块名称
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end
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endmodule
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