1322 lines
41 KiB
Python
1322 lines
41 KiB
Python
import array
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HOST_WRITE = 0
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HOST_READ = 1
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LVDS_WRITE = 2
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LVDS_READ = 3
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class ArrayUintRef:
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"""对 array 某个元素的引用代理"""
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def __init__(self, arr, index, t = 0):
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self.arr = arr
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self.index = index
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self.t = t
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@property
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def value(self):
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val = 0
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if self.t == 0:
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val = self.arr[self.index]
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elif self.t == 1:
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val = (self.arr[self.index]
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| (self.arr[self.index + 1] << 8))
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elif self.t == 2:
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val = (self.arr[self.index]
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| (self.arr[self.index + 1] << 8)
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| (self.arr[self.index + 2] << 16)
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| (self.arr[self.index + 3] << 24))
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#elif self.t == 3:
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else:
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val = (self.arr[self.index]
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| (self.arr[self.index + 1] << 8)
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| (self.arr[self.index + 2] << 16)
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| (self.arr[self.index + 3] << 24)
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| (self.arr[self.index + 4] << 32)
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| (self.arr[self.index + 5] << 40)
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| (self.arr[self.index + 6] << 48)
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| (self.arr[self.index + 7] << 56))
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return val
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@value.setter
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def value(self, val):
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self.arr[self.index] = (val & 0xff)
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if self.t >= 1:
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self.arr[self.index + 1] = ((val >> 8) & 0xff)
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if self.t >= 2:
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self.arr[self.index + 2] = ((val >> 16) & 0xff)
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self.arr[self.index + 3] = ((val >> 24) & 0xff)
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if self.t >= 3:
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self.arr[self.index + 4] = ((val >> 32) & 0xff)
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self.arr[self.index + 5] = ((val >> 40) & 0xff)
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self.arr[self.index + 6] = ((val >> 48) & 0xff)
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self.arr[self.index + 7] = ((val >> 56) & 0xff)
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#print('setter:', self.t)
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def __repr__(self):
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return f"ArrayUintRef(value={self.value})"
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class MemroyQueueMgr:
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class MemoryQueue:
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def __init__(self, mq):
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self.mq = mq
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self.data = list()
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def __getitem__(self, index):
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if len(self.data) == 0:
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if isinstance(index, slice):
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return list()[index]
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else:
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return 0
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val = self.data[0]
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if isinstance(index, slice):
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return val[index]
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else:
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if index < 2048:
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return val[index]
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else:
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return 0
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def __setitem__(self, index, value):
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if len(self.data) != 0:
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pass
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if index < 2048:
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self.data[0][index] = value
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def __len__(self):
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return len(self.data)
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def deq(self):
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if len(self.data) != 0:
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v = self.data.pop(0)
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return v
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else:
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return None
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def enq(self, item):
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if type(item) != array.array:
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print('Error, item type:', type(item))
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return
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else:
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self.data.append(item)
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def reset(self):
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self.data = list()
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def __init__(self, item_num):
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self.memory = list()
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self.item_num = item_num
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self.din = MemroyQueueMgr.MemoryQueue(self)
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self.dout = MemroyQueueMgr.MemoryQueue(self)
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self.reset()
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def reset(self):
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self.din.reset()
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self.dout.reset()
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self.memory = list()
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for i in range(self.item_num):
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self.memory.append(array.array('B', [0] * 2048))
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for i in range(self.item_num):
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self.din.enq(self.memory[i])
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def __getitem__(self, index):
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return self.dout[index]
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def __setitem__(self, index, value):
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self.din[index] = value
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def __len__(self):
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return len(self.dout)
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def enq_data(self):
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self.dout.enq(self.din.deq())
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def free_data(self):
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#这里
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self.din.enq(self.dout.deq())
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@staticmethod
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def clear(arr):
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if type(arr) != array.array:
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return
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for i in range(len(arr)): arr[i] = 0
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class device(object):
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def __init__(self):
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super().__init__()
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self.reset()
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def reset(self):
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self.reg = array.array('B', [0, ] * 2048)
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# 配置各SM的item数量（sm0~sm7）
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self.sm = dict()
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syncMemNum = [4, 4, 4, 4, 2, 2, 2, 2]
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for i in range(8):
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self.sm[f'mem{i}'] = MemroyQueueMgr(syncMemNum[i])
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self.sm[f'mem{i}_ctrl'] = ArrayUintRef(self.reg, 0x300 + i * 4)
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self.sm[f'mem{i}_item_num'] = ArrayUintRef(self.reg, 0x301 + i * 4)
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self.sm[f'mem{i}_len'] = ArrayUintRef(self.reg, 0x302 + i * 4, 1)
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#print(self.sm)
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self.ebmmu = dict()
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for i in range(16):
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self.ebmmu[f'va{i}'] = ArrayUintRef(self.reg, 0x200 + i * 0xa, 2)
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self.ebmmu[f'pa{i}'] = ArrayUintRef(self.reg, 0x204 + i * 0xa, 1)
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self.ebmmu[f'op{i}'] = ArrayUintRef(self.reg, 0x208 + i * 0xa, 0)
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self.ebmmu[f'en{i}'] = ArrayUintRef(self.reg, 0x209 + i * 0xa, 0)
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#看门狗
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self.watchdog = dict()
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self.watchdog["status"] = ArrayUintRef(self.reg, 0x400, 2)
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self.watchdog["enable"] = ArrayUintRef(self.reg, 0x404, 2)
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for i in range(18):
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self.watchdog[f"{i}"] = ArrayUintRef(self.reg, 0x408 + i * 4, 2)
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#事件
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self.event = dict()
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self.event['ctrl0'] = ArrayUintRef(self.reg, 0x500, 1)
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self.event['ctrl1'] = ArrayUintRef(self.reg, 0x502, 1)
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self.event['status0'] = ArrayUintRef(self.reg, 0x504, 1)
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self.event['status1'] = ArrayUintRef(self.reg, 0x506, 1)
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self.event['rise0'] = ArrayUintRef(self.reg, 0x508, 3)
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self.event['fall0'] = ArrayUintRef(self.reg, 0x510, 3)
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self.event['rise1'] = ArrayUintRef(self.reg, 0x518, 3)
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self.event['fall1'] = ArrayUintRef(self.reg, 0x520, 3)
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self.event['host_sm_w'] = ArrayUintRef(self.reg, 0x528, 3)
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self.event['host_sm_r'] = ArrayUintRef(self.reg, 0x530, 3)
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self.event['lvds_sm_w'] = ArrayUintRef(self.reg, 0x538, 3)
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self.event['lvds_sm_r'] = ArrayUintRef(self.reg, 0x540, 3)
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#主/从设备
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self.role = ArrayUintRef(self.reg, 0)
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#硬件版本号
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self.reg[1] = 0x1
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#硬件编码
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self.reg[2] = 0x4c
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self.reg[3] = 0x58
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self.reg[4] = 0x50
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self.reg[5] = 0x30
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self.reg[6] = 0x30
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self.reg[7] = 0x31
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#硬件接口
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self.reg[9] = 0x01
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#中断状态
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self.reg[0x73] = 0x80
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self.reg[0x77] = 0x80
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self.int_en = ArrayUintRef(self.reg, 0x70, 2)
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self.int_status = ArrayUintRef(self.reg, 0x74, 2)
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self.int_clear = ArrayUintRef(self.reg, 0x78, 2)
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self.int_mode = ArrayUintRef(self.reg, 0x7c, 1)
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#SYNC同步点
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self.sync_point = ArrayUintRef(self.reg, 0x130, 3)
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self.sync_point.value = 0xffffffffffffffff
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#print('sync_point', self.reg[0x130:0x138], hex(self.sync_point.value))
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'''
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self.reg[0x130] = 0xff
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self.reg[0x131] = 0xff
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self.reg[0x132] = 0xff
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self.reg[0x133] = 0xff
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self.reg[0x134] = 0xff
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self.reg[0x135] = 0xff
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self.reg[0x136] = 0xff
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self.reg[0x137] = 0xff
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'''
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self.__init_temp_regs()
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self.next_dev = None
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self.prev_dev = None
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def connect_next(self, dev):
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if isinstance(dev, device):
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self.next_dev = dev
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dev.prev_dev = self
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return True
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return False
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def __init_temp_regs(self):
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#临时寄存器
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#LVDS侧写入锁
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self.lvds_0x18 = 0x0
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self.lvds_0x19 = 0x0
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#RESET
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self.reset_0x40 = 0x0
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self.reset_0x41 = 0x0
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self.reset_0x42 = 0x0
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self.reset_0x43 = 0x0
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#交换上下行管脚
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self.swap_dir_0x4a = 0x0
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self.swap_dir_0x4b = 0x0
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#code_sel, 4b5b, 8b10b
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self.code_sel_0x4c = 0x0
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self.code_sel_0x4d = 0x0
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#cdr_type
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self.cdr_type_0x4e = 0x0
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self.cdr_type_0x4f = 0x0
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#int_status temp reg
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self.int_status = [0x0, 0x0, 0x0, 0x80]
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def hostwrite(self, addr, data):
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l = len(data)
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ret = False
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for k, v in enumerate(range(addr, addr+l)):
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ret = (self.__ctrl_regs_wr(HOST_WRITE, v, data[k])
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or self.__trans_ctrl_regs_wr(HOST_WRITE, v, data[k])
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or self.__reset_ctrl_regs_wr(HOST_WRITE, v, data[k])
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or self.__int_regs_wr(HOST_WRITE, v, data[k])
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or self.__stat_regs_wr(HOST_WRITE, v, data[k])
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or self.__link_regs_wr(HOST_WRITE, v, data[k])
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or self.__sync_regs_wr(HOST_WRITE, v, data[k])
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or self.__custom_def_regs_wr(HOST_WRITE, v, data[k])
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or self.__ebmmu_regs_wr(HOST_WRITE, v, data[k])
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or self.__sm_regs_wr(HOST_WRITE, v, data[k])
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or self.__watch_dog_regs_wr(HOST_WRITE, v, data[k])
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or self.__event_regs_wr(HOST_WRITE, v, data[k])
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)
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# self.__init_temp_regs()
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return ret
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def hostread(self, addr, l):
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data = [0, ] * l
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for k, v in enumerate(range(addr, addr+l)):
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if v < 2048:
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data[k] = self.reg[v]
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if v >= 2048:
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pass
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return data
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def trans_2_next_dev(self, packet):
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pass
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def trans_2_prev_dev(self, packet):
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pass
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def __ctrl_regs_wr(self, op, regaddr, val, *args):
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if 0x0 <= regaddr <= 0x19:
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pass
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else:
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return False
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if regaddr == 0x00:
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if op == HOST_WRITE:
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self.reg[regaddr] = val & 0xff
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elif op == LVDS_WRITE:
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pass
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elif (op == HOST_READ) or (op == LVDS_READ):
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val[args[0]] = self.reg[regaddr]
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else:
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pass
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elif regaddr == 0x01:
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# 硬件版本号，写入无效
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if (op == HOST_WRITE) or (op == LVDS_WRITE):
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pass
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elif (op == HOST_READ) or (op == LVDS_READ):
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val[args[0]] = self.reg[regaddr]
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else:
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pass
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elif 0x02 <= regaddr <= 0x07:
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# 硬件编码，写入无效
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if (op == HOST_WRITE) or (op == LVDS_WRITE):
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pass
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elif (op == HOST_READ) or (op == LVDS_READ):
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val[args[0]] = self.reg[regaddr]
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else:
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pass
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elif regaddr == 0x09:
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#硬件接口(0,1,2,3,4,5)
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if op == HOST_WRITE:
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self.reg[regaddr] = val & 0xff
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elif op == LVDS_WRITE:
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pass
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elif (op == HOST_READ) or (op == LVDS_READ):
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val[args[0]] = self.reg[regaddr]
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else:
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pass
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elif 0xa <= regaddr <= 0xb:
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#EasyBus站点地址
|
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if (op == HOST_READ) or (op == LVDS_READ):
|
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if self.role.value == 2:
|
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val[args[0]] = self.reg[regaddr]
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else:
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pass
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elif 0x10 <= regaddr <= 0x17:
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#硬件唯一编码，写入无效
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if (op == HOST_WRITE) or (op == LVDS_WRITE):
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pass
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elif (op == HOST_READ) or (op == LVDS_READ):
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val[args[0]] = self.reg[regaddr]
|
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else:
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pass
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elif 0x18 <= regaddr <= 0x19:
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#lvds写入锁
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if (op == HOST_WRITE) or (op == LVDS_WRITE):
|
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if self.role.value == 1:
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pass
|
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elif self.role.value == 2:
|
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if regaddr == 0x18:
|
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self.lvds_0x18 = val & 0x1
|
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elif regaddr == 0x19:
|
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if val == 0x58:
|
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self.reg[regaddr] = self.lvds_0x18
|
||
else:
|
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pass
|
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elif (op == HOST_READ) or (op == LVDS_READ):
|
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val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
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|
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else:
|
||
return False
|
||
|
||
return True
|
||
|
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def __trans_ctrl_regs_wr(self, op, regaddr, val, *args):
|
||
if 0x20 <= regaddr <= 0x25:
|
||
pass
|
||
else:
|
||
return False
|
||
|
||
if (self.role.value >= 2) or (self.role.value < 1):
|
||
return True
|
||
|
||
if regaddr == 0x20:
|
||
if op == HOST_WRITE:
|
||
self.reg[regaddr] = val & 0xff
|
||
en_tx = (val & 0x1)
|
||
buf_no = (val >> 1) & 0x3
|
||
#buf_rx = (val >> 3) & 0x3
|
||
if en_tx == 0x1:
|
||
self.reg[regaddr] = self.reg[regaddr] & 0xfe
|
||
#发送数据
|
||
pass
|
||
elif op == LVDS_WRITE:
|
||
pass
|
||
elif (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
elif (op == LVDS_READ):
|
||
#val[args[0]] = 0
|
||
pass
|
||
else:
|
||
pass
|
||
|
||
elif 0x22 <= regaddr <= 0x23:
|
||
if op == HOST_WRITE:
|
||
self.reg[0x22] = 0
|
||
self.reg[0x23] = 0
|
||
elif op == LVDS_WRITE:
|
||
pass
|
||
elif (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
elif (op == LVDS_READ):
|
||
pass
|
||
else:
|
||
pass
|
||
|
||
elif 0x24 <= regaddr <= 0x25:
|
||
if op == HOST_WRITE:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif op == LVDS_WRITE:
|
||
pass
|
||
elif (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
elif (op == LVDS_READ):
|
||
pass
|
||
else:
|
||
pass
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
def __reset_ctrl_regs_wr(self, op, regaddr, val, *args):
|
||
if 0x40 <= regaddr <= 0x55:
|
||
pass
|
||
else:
|
||
return False
|
||
|
||
#EasyBus复位
|
||
if 0x40 <= regaddr <= 0x43:
|
||
if (op == LVDS_WRITE) and (op == LVDS_READ):
|
||
pass
|
||
|
||
elif op == HOST_WRITE:
|
||
if regaddr == 0x40:
|
||
self.reset_0x40 = val & 0x1
|
||
elif regaddr == 0x41:
|
||
self.reset_0x41 = 0
|
||
elif regaddr == 0x42:
|
||
self.reset_0x42 = val & 0xff
|
||
elif regaddr == 0x43:
|
||
self.reset_0x43 = val & 0xff
|
||
else:
|
||
pass
|
||
|
||
if (self.reset_0x42 == 0x66) and (self.reset_0x43 == 0x79):
|
||
if self.reset_0x40 == 0x1:
|
||
#重启芯片
|
||
self.reset_0x42 = 0
|
||
self.reset_0x43 = 0
|
||
#self.reset_0x40 = 0
|
||
#self.reset_0x41 = 0
|
||
else:
|
||
pass
|
||
elif op == HOST_READ:
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#交换上下行管脚
|
||
elif 0x4a <= regaddr <= 0x4b:
|
||
if (op == LVDS_WRITE) and (op == LVDS_READ):
|
||
pass
|
||
|
||
elif op == HOST_WRITE:
|
||
if regaddr == 0x4a:
|
||
self.swap_dir_0x4a = val & 0xff
|
||
elif regaddr == 0x4b:
|
||
self.swap_dir_0x4b = val & 0xff
|
||
if self.swap_dir_0x4b == 0x58:
|
||
self.reg[0x4a] = self.swap_dir_0x4a
|
||
self.swap_dir_0x4b = 0x0
|
||
#进行管脚交换
|
||
else:
|
||
pass
|
||
else:
|
||
pass
|
||
elif op == HOST_READ:
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#4b5b,8b10b选择
|
||
#BIT0:0,选择8b10b编码；1选择4b5b编码
|
||
#BIT15-BIT8:key，当KEY = 0x59，且BIT0为1时，4b5b；BIT0为0时，8b10b。
|
||
#读取时KEY始终为0。KEY不正确，不响应修改
|
||
elif 0x4c <= regaddr <= 0x4d:
|
||
if (op == LVDS_WRITE) and (op == LVDS_READ):
|
||
pass
|
||
|
||
elif op == HOST_WRITE:
|
||
if regaddr == 0x4c:
|
||
self.code_sel_0x4c = val & 0xff
|
||
elif regaddr == 0x4d:
|
||
self.code_sel_0x4d = val & 0xff
|
||
if self.code_sel_0x4d == 0x59:
|
||
self.reg[0x4c] = self.code_sel_0x4c
|
||
self.code_sel_0x4d = 0
|
||
#切换编码
|
||
else:
|
||
pass
|
||
else:
|
||
pass
|
||
elif op == HOST_READ:
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#CDR参数
|
||
elif 0x4e <= regaddr <= 0x4f:
|
||
if (op == LVDS_WRITE) and (op == LVDS_READ):
|
||
pass
|
||
|
||
elif op == HOST_WRITE:
|
||
if regaddr == 0x4e:
|
||
self.cdr_type_0x4e = val & 0xff
|
||
elif regaddr == 0x4f:
|
||
self.cdr_type_0x4f = val & 0xff
|
||
if self.cdr_type_0x4f == 0x60:
|
||
self.reg[0x4e] = self.cdr_type_0x4e
|
||
self.cdr_type_0x4f = 0x0
|
||
#执行cdr参数
|
||
else:
|
||
pass
|
||
else:
|
||
pass
|
||
elif op == HOST_READ:
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#4倍频分频系数
|
||
elif regaddr == 0x55:
|
||
if (op == LVDS_WRITE) and (op == LVDS_READ):
|
||
pass
|
||
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
|
||
elif op == HOST_READ:
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
def __int_regs_wr(self, op, regaddr, val, *args):
|
||
if 0x70 <= regaddr <= 0x7d:
|
||
pass
|
||
else:
|
||
return False
|
||
|
||
#中断使能
|
||
if 0x70 <= regaddr <= 0x73:
|
||
if (op == LVDS_WRITE):
|
||
pass
|
||
elif op == HOST_WRITE:
|
||
self.reg[regaddr] = val & 0xff
|
||
self.reg[0x73] = self.reg[0x73] | 0x80
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#中断状态
|
||
elif 0x74 <= regaddr <= 0x77:
|
||
#只读
|
||
#warning
|
||
if (op == LVDS_WRITE) or (op == HOST_WRITE):
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#中断状态清除
|
||
elif 0x78 <= regaddr <= 0x7b:
|
||
if (op == LVDS_WRITE):
|
||
pass
|
||
elif op == HOST_WRITE:
|
||
self.reg[regaddr - 0x4] = (~val) & self.reg[regaddr - 0x4]
|
||
self.int_status[regaddr - 0x78] = (~val) & self.int_status[regaddr - 0x78]
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#中断模式
|
||
elif 0x7c <= regaddr <= 0x7d:
|
||
if (op == LVDS_WRITE):
|
||
pass
|
||
elif op == HOST_WRITE:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
def __stat_regs_wr(self, op, regaddr, val, *args):
|
||
#统计
|
||
#下行接收错误计数器（包括包不完全、CDR、CRC、超时）
|
||
if 0x80 <= regaddr <= 0x81:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x80] = 0
|
||
regaddr[0x81] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
elif 0x82 <= regaddr <= 0x83:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x82] = 0
|
||
regaddr[0x83] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0x84 <= regaddr <= 0x85:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x84] = 0
|
||
regaddr[0x85] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0x86 <= regaddr <= 0x87:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x86] = 0
|
||
regaddr[0x87] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0x88 <= regaddr <= 0x89:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x88] = 0
|
||
regaddr[0x89] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0x8a <= regaddr <= 0x8b:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x8a] = 0
|
||
regaddr[0x8b] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0x8c <= regaddr <= 0x8f:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x8c] = 0
|
||
regaddr[0x8f] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0x90 <= regaddr <= 0x97:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0x90] = 0
|
||
regaddr[0x91] = 0
|
||
regaddr[0x92] = 0
|
||
regaddr[0x93] = 0
|
||
regaddr[0x94] = 0
|
||
regaddr[0x95] = 0
|
||
regaddr[0x96] = 0
|
||
regaddr[0x97] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#上行
|
||
elif 0xa0 <= regaddr <= 0xa1:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xa0] = 0
|
||
regaddr[0xa1] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0xa2 <= regaddr <= 0xa3:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xa2] = 0
|
||
regaddr[0xa3] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0xa4 <= regaddr <= 0xa5:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xa4] = 0
|
||
regaddr[0xa5] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0xa6 <= regaddr <= 0xa7:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xa6] = 0
|
||
regaddr[0xa7] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0xa8 <= regaddr <= 0xa9:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xa8] = 0
|
||
regaddr[0xa9] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0xaa <= regaddr <= 0xab:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xaa] = 0
|
||
regaddr[0xab] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0xac <= regaddr <= 0xaf:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xac] = 0
|
||
regaddr[0xad] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif 0xb0 <= regaddr <= 0xb7:
|
||
if (op == LVDS_WRITE):
|
||
regaddr[0xb0] = 0
|
||
regaddr[0xb1] = 0
|
||
regaddr[0xb2] = 0
|
||
regaddr[0xb3] = 0
|
||
regaddr[0xb4] = 0
|
||
regaddr[0xb5] = 0
|
||
regaddr[0xb6] = 0
|
||
regaddr[0xb7] = 0
|
||
elif op == HOST_WRITE:
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
def __link_regs_wr(self, op, regaddr, val, *args):
|
||
#两个寄存器都是只读
|
||
#链路状态
|
||
if 0xc0 <= regaddr <= 0xc1:
|
||
if (op == LVDS_WRITE) or (op == HOST_WRITE):
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
#右侧设备地址
|
||
elif 0xc2 <= regaddr <= 0xc3:
|
||
if (op == LVDS_WRITE) or (op == HOST_WRITE):
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
|
||
def __sync_regs_wr(self, op, regaddr, val, *args):
|
||
#同步
|
||
#这里注意一个问题，主站是否要考虑lvds侧锁不锁的问题
|
||
'''
|
||
if 0x0100 <= regaddr <= 0x107:
|
||
pass
|
||
elif 0x0108 <= regaddr <= 0x10f:
|
||
pass
|
||
elif 0x0110 <= regaddr <= 0x113:
|
||
pass
|
||
elif 0x0114 <= regaddr <= 0x117:
|
||
pass
|
||
elif 0x0118 <= regaddr <= 0x11f:
|
||
pass
|
||
'''
|
||
if 0x0100 <= regaddr <= 0x11f:
|
||
if (op == LVDS_WRITE) or (op == HOST_WRITE):
|
||
pass
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
'''
|
||
elif 0x0120 <= regaddr <= 0x121:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif 0x0122 <= regaddr <= 0x123:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif 0x0124 <= regaddr <= 0x125:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif 0x0126 <= regaddr <= 0x127:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif 0x0128 <= regaddr <= 0x129:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
'''
|
||
elif 0x0120 <= regaddr <= 0x129:
|
||
if (op == LVDS_WRITE):
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_WRITE):
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
|
||
'''
|
||
elif 0x0130 <= regaddr <= 0x137:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
|
||
elif 0x0138 <= regaddr <= 0x13b:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif 0x013c <= regaddr <= 0x13f:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif 0x0140 <= regaddr <= 0x143:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif 0x0144 <= regaddr <= 0x147:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
|
||
elif 0x0148 <= regaddr <= 0x14f:
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
'''
|
||
elif 0x0130 <= regaddr <= 0x14f:
|
||
if (op == LVDS_WRITE):
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_WRITE):
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_READ) or (op == LVDS_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
def __custom_def_regs_wr(self, op, regaddr, val, *args):
|
||
if 0x180 <= regaddr <= 0x1FF:
|
||
if self.role.value == 2:
|
||
if (op == LVDS_WRITE) or (op == HOST_WRITE):
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
else:
|
||
pass
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
def __ebmmu_regs_wr(self, op, regaddr, val, *args):
|
||
ebmmu_base = 0x200
|
||
ebmmu_no = 16
|
||
|
||
for i in range(ebmmu_no):
|
||
if (ebmmu_base + i * 0xa) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x3):
|
||
if self.role.value == 2:
|
||
if (op == LVDS_WRITE):
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_WRITE):
|
||
pass
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif ((ebmmu_base + i * 0xa) + 0x4) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x5):
|
||
if self.role.value == 2:
|
||
if (op == LVDS_WRITE):
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_WRITE):
|
||
pass
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif ((ebmmu_base + i * 0xa) + 0x6) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x7):
|
||
if self.role.value == 2:
|
||
if (op == LVDS_WRITE):
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_WRITE):
|
||
pass
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif regaddr == ((ebmmu_base + i * 0xa) + 0x8):
|
||
if self.role.value == 2:
|
||
if (op == LVDS_WRITE):
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_WRITE):
|
||
pass
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif regaddr == ((ebmmu_base + i * 0xa) + 0x9):
|
||
if self.role.value == 2:
|
||
if (op == LVDS_WRITE):
|
||
if (self.reg[0x18] & 0x1) == 0x1:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == HOST_WRITE):
|
||
pass
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
else:
|
||
continue
|
||
|
||
return True
|
||
|
||
return False
|
||
|
||
def __sm_regs_wr(self, op, regaddr, val, *args):
|
||
#数据缓冲区描述寄存器组
|
||
'''
|
||
self.sm[f'mem{i}'] = MemroyQueueMgr(syncMemNum[i])
|
||
self.sm[f'mem{i}_ctrl'] = ArrayUintRef(self.reg, 0x300 + i * 4)
|
||
self.sm[f'mem{i}_item_num'] = ArrayUintRef(self.reg, 0x301 + i * 4)
|
||
self.sm[f'mem{i}_len'] = ArrayUintRef(self.reg, 0x302 + i * 4, 1)
|
||
'''
|
||
for i in range(8):
|
||
if regaddr == (0x300 + i * 0x4):
|
||
if (op == LVDS_WRITE):
|
||
pass
|
||
elif (op == HOST_WRITE):
|
||
self.sm[f'mem{i}_ctrl'].value = 0
|
||
#复位
|
||
self.sm[f'mem{i}'].reset()
|
||
self.sm[f'mem{i}_item_num'].value = 0
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif regaddr == (0x301 + i * 0x4):
|
||
if (op == LVDS_WRITE):
|
||
pass
|
||
elif (op == HOST_WRITE):
|
||
pass
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
elif (0x302 + i * 0x4) <= regaddr <= (0x303 + i * 0x4):
|
||
if (op == LVDS_WRITE) or (op == HOST_WRITE):
|
||
if self.sm[f'mem{i}_item_num'].value == 0:
|
||
self.reg[regaddr] = val & 0xff
|
||
elif (op == LVDS_READ) or (op == HOST_READ):
|
||
val[args[0]] = self.reg[regaddr]
|
||
else:
|
||
pass
|
||
else:
|
||
continue
|
||
|
||
return True
|
||
|
||
for i in range(8):
|
||
if self.role.value == 1:
|
||
if ((op == LVDS_WRITE)) or ((op == HOST_WRITE)):
|
||
if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800):
|
||
self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] = val
|
||
if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value:
|
||
self.sm[f'mem{i}'].enq_data()
|
||
self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}'])
|
||
return True
|
||
elif ((op == LVDS_READ)) or ((op == HOST_READ)):
|
||
if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800):
|
||
val[args[0]] = self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800]
|
||
if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value:
|
||
self.sm[f'mem{i}'].free_data()
|
||
self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}'])
|
||
return True
|
||
else:
|
||
pass
|
||
elif self.role.value == 2:
|
||
if ((op == LVDS_WRITE)) or ((op == HOST_WRITE)):
|
||
if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800):
|
||
self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] = val
|
||
if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value:
|
||
self.sm[f'mem{i}'].enq_data()
|
||
self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}'])
|
||
return True
|
||
elif ((op == LVDS_READ)) or ((op == HOST_READ)):
|
||
if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800):
|
||
val[args[0]] = self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800]
|
||
if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value:
|
||
self.sm[f'mem{i}'].free_data()
|
||
self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}'])
|
||
return True
|
||
else:
|
||
pass
|
||
else:
|
||
pass
|
||
|
||
return False
|
||
|
||
|
||
def __watch_dog_regs_wr(self, op, regaddr, val):
|
||
#看门狗
|
||
if 0x400 <= regaddr <= 0x403:
|
||
pass
|
||
elif 0x404 <= regaddr <= 0x407:
|
||
pass
|
||
elif 0x408 <= regaddr <= 0x40B:
|
||
pass
|
||
elif 0x40C <= regaddr <= 0x40F:
|
||
pass
|
||
|
||
elif 0x410 <= regaddr <= 0x413:
|
||
pass
|
||
elif 0x414 <= regaddr <= 0x417:
|
||
pass
|
||
elif 0x418 <= regaddr <= 0x40B:
|
||
pass
|
||
elif 0x41C <= regaddr <= 0x41F:
|
||
pass
|
||
|
||
elif 0x420 <= regaddr <= 0x423:
|
||
pass
|
||
elif 0x424 <= regaddr <= 0x427:
|
||
pass
|
||
elif 0x428 <= regaddr <= 0x42B:
|
||
pass
|
||
elif 0x42C <= regaddr <= 0x42F:
|
||
pass
|
||
|
||
elif 0x430 <= regaddr <= 0x433:
|
||
pass
|
||
elif 0x434 <= regaddr <= 0x437:
|
||
pass
|
||
elif 0x438 <= regaddr <= 0x43B:
|
||
pass
|
||
elif 0x43C <= regaddr <= 0x43F:
|
||
pass
|
||
|
||
elif 0x440 <= regaddr <= 0x443:
|
||
pass
|
||
elif 0x444 <= regaddr <= 0x447:
|
||
pass
|
||
elif 0x448 <= regaddr <= 0x44B:
|
||
pass
|
||
elif 0x44C <= regaddr <= 0x44F:
|
||
pass
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
def __event_regs_wr(self, op, regaddr, val):
|
||
if 0x500 <= regaddr <= 0x501:
|
||
pass
|
||
elif 0x502 <= regaddr <= 0x503:
|
||
pass
|
||
elif 0x504 <= regaddr <= 0x505:
|
||
pass
|
||
elif 0x506 <= regaddr <= 0x507:
|
||
pass
|
||
elif 0x508 <= regaddr <= 0x50F:
|
||
pass
|
||
elif 0x510 <= regaddr <= 0x517:
|
||
pass
|
||
elif 0x518 <= regaddr <= 0x51F:
|
||
pass
|
||
elif 0x520 <= regaddr <= 0x527:
|
||
pass
|
||
elif 0x528 <= regaddr <= 0x52F:
|
||
pass
|
||
elif 0x530 <= regaddr <= 0x537:
|
||
pass
|
||
elif 0x538 <= regaddr <= 0x53F:
|
||
pass
|
||
elif 0x540 <= regaddr <= 0x547:
|
||
pass
|
||
else:
|
||
return False
|
||
|
||
return True
|
||
|
||
|
||
if __name__ == '__main__':
|
||
m = device()
|
||
d0 = device()
|
||
d1 = device()
|
||
d2 = device()
|
||
d3 = device()
|
||
|
||
m.connect_next(d0)
|
||
d0.connect_next(d1)
|
||
d1.connect_next(d2)
|
||
d2.connect_next(d3)
|
||
|
||
m.hostwrite(0, [1, ])
|
||
d0.hostwrite(0, [2, ])
|
||
d1.hostwrite(0, [2, ])
|
||
d2.hostwrite(0, [2, ])
|
||
d3.hostwrite(0, [2, ])
|
||
|
||
data = m.hostread(0, 128)
|
||
print(data)
|
||
data = d0.hostread(0, 128)
|
||
print(data)
|
||
|
||
'''
|
||
m = device()
|
||
d0 = device()
|
||
d1 = device()
|
||
d2 = device()
|
||
d3 = device()
|
||
|
||
m.connect_next(d0)
|
||
d0.connect_next(d1)
|
||
d1.connect_next(d2)
|
||
d2.connect_next(d3)
|
||
|
||
m.hostwrite(0, [2,])
|
||
data = m.hostread(0, 128)
|
||
#print(data)
|
||
data = m.hostread(0x74, 4)
|
||
#print(data)
|
||
m.hostwrite(0x78, [0xff, 0xff, 0xff, 0xff])
|
||
data = m.hostread(0x74, 4)
|
||
#print(data)
|
||
|
||
|
||
sm0 = MemroyQueueMgr(4)
|
||
sm0[0] = 1
|
||
sm0[1] = 2
|
||
sm0[2] = 3
|
||
sm0[3] = 4
|
||
print(len(sm0))
|
||
sm0.enq_data()
|
||
print(len(sm0))
|
||
sm0[0] = 4
|
||
sm0[1] = 3
|
||
sm0[2] = 2
|
||
sm0[3] = 1
|
||
sm0.enq_data()
|
||
print(len(sm0))
|
||
|
||
#print(len(sm0.din))
|
||
#print(len(sm0.dout))
|
||
|
||
print(sm0[:4], len(sm0))
|
||
sm0.free_data()
|
||
print(sm0[:4], len(sm0))
|
||
sm0.free_data()
|
||
print(sm0[:4], len(sm0))
|
||
#sm0.clear(sm0.dout.data[0])
|
||
#print(sm0.dout.data[0][:4])
|
||
sm0.reset()
|
||
|
||
sm0[0] = 1
|
||
sm0[1] = 2
|
||
sm0[2] = 3
|
||
sm0[3] = 4
|
||
print(len(sm0))
|
||
sm0.enq_data()
|
||
print(len(sm0))
|
||
sm0[0] = 4
|
||
sm0[1] = 3
|
||
sm0[2] = 2
|
||
sm0[3] = 1
|
||
sm0.enq_data()
|
||
print(len(sm0))
|
||
|
||
#print(len(sm0.din))
|
||
#print(len(sm0.dout))
|
||
|
||
print(sm0[:4], len(sm0))
|
||
sm0.free_data()
|
||
print(sm0[:4], len(sm0))
|
||
sm0.free_data()
|
||
print(sm0[:4], len(sm0))
|
||
|
||
|
||
def testfunc(op):
|
||
if op == 0:
|
||
return False, 1, 2, 3
|
||
else:
|
||
return True, 3, 2, 1
|
||
|
||
def testfunc2(op, val, *args):
|
||
if isinstance(val, list):
|
||
val[args[0]] = op
|
||
return True
|
||
|
||
|
||
a = testfunc(0)
|
||
b = testfunc(1)
|
||
print(a)
|
||
print(b)
|
||
|
||
arr = [1, 2, 3]
|
||
|
||
print(arr)
|
||
testfunc2(100, arr, 0)
|
||
print(arr)
|
||
'''
|