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eb001
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45e46b2d46dc9998cb4193f458e8b6af51259de5
eb001
/
src
/
main
/
verilog
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RuigeLee
9c56c611e2
修改芯片码
2024-05-11 17:21:05 +08:00
..
backBoardMstTop.v
使用测试IO上跳沿替代写有效的ctrlTransmit 写入,效果很好,可以认为,当前有问题的是寄存器写入
2024-03-21 19:08:34 +08:00
backBoardSlvTop.v
输出IO扩展为16个
2024-03-06 17:10:51 +08:00
defineParam.v
修改芯片码
2024-05-11 17:21:05 +08:00
di16_top.v
修改芯片码
2024-05-11 17:21:05 +08:00
do16_top.v
修改芯片码
2024-05-11 17:21:05 +08:00
oser_rst.v
test pass
2023-09-14 19:16:17 +08:00