112 lines
3.3 KiB
Makefile
112 lines
3.3 KiB
Makefile
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.PHONY: compile
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compile:
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rm -rf ./generated/
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rm -rf ./rocket-chip/vsim/generated-src/
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mkdir -p ./generated/
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cd ./rocket-chip/ && rm -f rocketchip.jar
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cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.UserFPGAConfig
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cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v
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cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v
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# sbt "test:runMain test.testModule"
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back:
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sbt "test:runMain test.testModule"
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cp ./src/main/verilog/backBoardMstTop.v ./generated/
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cp ./src/main/verilog/backBoardSlvTop.v ./generated/
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cp ./src/main/verilog/oser_rst.v ./generated/
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ef:
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sbt "test:runMain test.testModule"
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VSimTop:
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rm -rf ./tb/build/
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mkdir -p ./tb/build/
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verilator -Wno-fatal \
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--timescale "1 ns / 1 ps" \
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-y ${PWD}/tb/ \
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-y ${PWD}/tb/vtb/ \
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--top-module SimTop \
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--trace-fst \
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--cc ./tb/behav_srams.v \
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--cc ./tb/UserFPGAConfig.v \
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--cc ./tb/vtb/SimTop.v \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_DELAY=0 \
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+define+USE_POWER_PINS \
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--exe --build \
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${PWD}/tb/sim_main.cpp \
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-Mdir ./tb/build/ \
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-j 30
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test:
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./tb/build/VSimTop -w -l -f ./tb/sw/build/test
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sw:
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
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-c ./tb/sw/src/main.c \
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-o ./tb/sw/build/main.o
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
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-c ./tb/sw/axi_uart/uart.c \
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-o ./tb/sw/build/uart.o
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src -I ./tb/sw/axi_gpio -I ./tb/sw/axi_uart -I ./tb/sw/axi_timer \
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-c ./tb/sw/src/startup.S \
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-o ./tb/sw/build/startup.o
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riscv64-unknown-elf-gcc -Os -ggdb -march=rv32im -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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-T ./tb/sw/linker.lds \
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./tb/sw/build/startup.o \
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./tb/sw/build/uart.o \
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./tb/sw/build/main.o \
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-o ./tb/sw/build/test.elf
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riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/test.elf ./tb/sw/build/test.bin
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riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata ./tb/sw/build/test.elf > ./tb/sw/build/test.dump
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riscv64-unknown-elf-objcopy -O verilog ./tb/sw/build/test.elf ./tb/sw/build/test.verilog
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sed -i 's/@800/@000/g' ./tb/sw/build/test.verilog
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fst:
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gtkwave ./tb/build/wave.fst &
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VSimBack:
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rm -rf ./tb/build/
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mkdir -p ./tb/build/
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verilator -Wno-fatal \
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--timescale "1 ns / 1 ps" \
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-y ${PWD}/tb/ \
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-y ${PWD}/generated/ \
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--top-module BackPlaneChainTest \
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--trace-fst \
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--cc ./generated/BackPlaneChainTest.v \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_DELAY=0 \
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--exe --build \
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${PWD}/tb/sim_backChain.cpp \
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-Mdir ./tb/build/ \
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-j 30
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