1030 lines
41 KiB
Scala
1030 lines
41 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class FrameHeader extends Bundle{
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val frameLenAim = UInt(12.W) //帧长度目标
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val frameStyle = UInt(2.W) //包类型
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val frameInfo = UInt(16.W) //其它信息，如probe
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}
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class SubMsgHeader extends Bundle{
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val devIndex = UInt(14.W) // 子报文中设备索引
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val style = UInt(2.W) // 子报文类型
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val address = UInt(16.W) //子报文地址
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val operator = UInt(4.W) //子报文命令类型
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val length = UInt(12.W) //子报文负载长度
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def isSeqIndex = style === 0.U
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def isLgcIndex = style === 2.U
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}
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class SubMsgTail extends Bundle{
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val workCnt = UInt(16.W) //子报文工作计数
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}
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// class ShareSRAMIO extends Bundle{
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// val addr = Input(UInt(15.W))
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// val dataw = Input( UInt(8.W) )
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// val datar = Output( UInt(8.W) )
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// val enw = Input(Bool())
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// val enr = Input(Bool())
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// }
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class SlaveParserIO extends Bundle{
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val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
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val downOut = Decoupled(new AXIS_Bundle(8))
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val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
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val upOut = Decoupled(new AXIS_Bundle(8))
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val sram_w = Vec( 4, Flipped(new SRAM2kWRIO))
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val sram_r = Vec( 4, Flipped(new SRAM2kRDIO))
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val dSMenq = Output( Vec(4, Bool()) )
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val uSMdeq = Output( Vec(4, Bool()) )
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val localDevIndex = Output(UInt(16.W))
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//开放链路寄存器组给interface
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// val isDevOnLeft = Output(UInt(2.W))
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// val isDevOnLeftModify = Output(Bool())
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// val indexOfLeftDev = Output(UInt(14.W))
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val isDevOnRight = Output(UInt(2.W))
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val isDevOnRightModify = Output(Bool())
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val indexOfRightDev = Output(UInt(14.W))
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val mstDeltaTimeStamp = Output(UInt(32.W))
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val slvDeltaTime = Output(UInt(32.W))
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val deltaFinal = Output(UInt(64.W))
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val isLoop = Output(Bool())
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val cReg = Input(new CommonRegisterBundle)
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val sReg = Input(new SlaveRegisterBundle)
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val lvds = new RegAccessInterfaceIO
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val intHWTrig = Output(Vec(2, Bool()))
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val intHWClr = Input (Vec(2, Bool()))
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val downRecStat = Output(new Stat_IO_Bundle)
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val upRecStat = Output(new Stat_IO_Bundle)
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}
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abstract class SlaveParserBase extends Module with RequireAsyncReset{
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val io: SlaveParserIO = IO(new SlaveParserIO)
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val sReg = io.sReg
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val FRAME_STYLE_COMMON = 0.U
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val FRAME_STYLE_PROBE = 1.U
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val SUBMSG_OPERATOR_UNIREAD = 0.U
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val SUBMSG_OPERATOR_UNIWRITE = 1.U
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val SUBMSG_OPERATOR_UNIRDWR = 2.U
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val SUBMSG_OPERATOR_INDEX = "hb".U
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val SUBMSG_OPERATOR_SYNC = "hc".U
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val SUBMSG_OPERATOR_BOARDREAD = "hd".U
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val SUBMSG_OPERATOR_BOARDWRITE = "he".U
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val SUBMSG_OPERATOR_BOARDRDWR = "hf".U
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val STATE_IDLE = 0.U //空闲
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val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
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val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
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val STATE_PAYLOAD_DATA = 3.U //子报文数据
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val STATE_SUBMSG_TAIL = 4.U
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val STATE_CRC = 5.U //CRC校验
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val STATE_ERROR = 6.U //
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val STATE_WAIT = 7.U
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val downRecParser = Module(new SlaveRecParser)
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val upRecParser = Module(new SlaveRecParser)
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val downSendGen = Module(new SlaveSendGen)
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val upSendGen = Module(new SlaveSendGen)
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val isReadyToProbe = RegInit(false.B)
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val isAckProbe = RegInit(false.B)
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val isLastDevice: Bool = RegInit(true.B)
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io.isDevOnRight := Mux( isLastDevice, "b00".U, "b01".U )
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val isDevOnRightModify = RegInit(false.B); io.isDevOnRightModify := isDevOnRightModify
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val indexOfRightDev = RegInit(0.U(14.W)); io.indexOfRightDev := indexOfRightDev
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val localDevIndex = RegInit(0.U(14.W)); io.localDevIndex := localDevIndex //当前设备索引
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//处理主报文
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downSendGen.io.frameReq.valid := downRecParser.io.frameReq.fire
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assert( ~(downSendGen.io.frameReq.valid & ~downSendGen.io.frameReq.ready) )
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{
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downSendGen.io.frameReq.bits := downRecParser.io.frameReq.bits
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//voerride
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downSendGen.io.frameReq.bits.frameInfo := localDevIndex
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}
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val upFrameProbeInfo: FrameHeader = Wire(new FrameHeader)
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upFrameProbeInfo.frameLenAim := 0.U //帧长度目标
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upFrameProbeInfo.frameStyle := FRAME_STYLE_PROBE //包类型
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upFrameProbeInfo.frameInfo := localDevIndex //其它信息，如probe
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upSendGen.io.frameReq.valid :=
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(upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON) |
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isAckProbe
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assert( ~(upSendGen.io.frameReq.valid & ~upSendGen.io.frameReq.ready) )
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assert( ~(upRecParser.io.frameReq.fire & isAckProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
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upSendGen.io.frameReq.bits := Mux1H(Seq(
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upRecParser.io.frameReq.fire -> upRecParser.io.frameReq.bits, //上行转发
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isAckProbe -> upFrameProbeInfo, //上行探针
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))
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////////////////////////////////////////
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//子报文
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val isDownSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isUpSubMsgHeadValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isDownSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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val isUpSubMsgTailValid = for( _ <- 0 until 2 ) yield { RegInit(false.B) }
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//接收子报文
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val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) } //子报文头
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val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) }
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val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) } //子报文头
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val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) }
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val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
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val upRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) }
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val isDownRecPing = RegInit(false.B)
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val isUpRecPing = RegInit(false.B)
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//下行接收
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when( downRecParser.io.subMsgHeadReq.fire ){
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when( isDownRecPing ){
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downSubMsgHeadInfo(0).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex
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downSubMsgHeadInfo(0).style := downRecParser.io.subMsgHeadReq.bits.style
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downSubMsgHeadInfo(0).address := downRecParser.io.subMsgHeadReq.bits.address
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downSubMsgHeadInfo(0).operator := downRecParser.io.subMsgHeadReq.bits.operator
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downSubMsgHeadInfo(0).length := downRecParser.io.subMsgHeadReq.bits.length
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downSubMsgHeadInfo(0).source := 0.U
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} .otherwise{ //pong
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downSubMsgHeadInfo(1).devIndex := downRecParser.io.subMsgHeadReq.bits.devIndex
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downSubMsgHeadInfo(1).style := downRecParser.io.subMsgHeadReq.bits.style
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downSubMsgHeadInfo(1).address := downRecParser.io.subMsgHeadReq.bits.address
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downSubMsgHeadInfo(1).operator := downRecParser.io.subMsgHeadReq.bits.operator
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downSubMsgHeadInfo(1).length := downRecParser.io.subMsgHeadReq.bits.length
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downSubMsgHeadInfo(1).source := 1.U
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}
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}
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when( downRecParser.io.subMsgTailReq.fire ){
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when( isDownRecPing ){
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downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt
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} .otherwise{ //pong
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downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt
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}
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}
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when( isDownRecPing ){ //req fire 后
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downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
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downRecFifo(0).io.enq.bits := downRecParser.io.data.bits
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downRecParser.io.data.ready := downRecFifo(0).io.enq.ready
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downRecFifo(1).io.enq.valid := false.B
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downRecFifo(1).io.enq.bits := 0.U
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} .otherwise{
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downRecFifo(0).io.enq.valid := false.B
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downRecFifo(0).io.enq.bits := 0.U
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downRecFifo(1).io.enq.valid := downRecParser.io.data.valid
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downRecFifo(1).io.enq.bits := downRecParser.io.data.bits
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downRecParser.io.data.ready := downRecFifo(1).io.enq.ready
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}
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//上行接收
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when( upRecParser.io.subMsgHeadReq.fire ){
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when( isUpRecPing ){
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upSubMsgHeadInfo(0).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex
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upSubMsgHeadInfo(0).style := upRecParser.io.subMsgHeadReq.bits.style
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upSubMsgHeadInfo(0).address := upRecParser.io.subMsgHeadReq.bits.address
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upSubMsgHeadInfo(0).operator := upRecParser.io.subMsgHeadReq.bits.operator
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upSubMsgHeadInfo(0).length := upRecParser.io.subMsgHeadReq.bits.length
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upSubMsgHeadInfo(0).source := 0.U
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} .otherwise{
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upSubMsgHeadInfo(1).devIndex := upRecParser.io.subMsgHeadReq.bits.devIndex
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upSubMsgHeadInfo(1).style := upRecParser.io.subMsgHeadReq.bits.style
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upSubMsgHeadInfo(1).address := upRecParser.io.subMsgHeadReq.bits.address
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upSubMsgHeadInfo(1).operator := upRecParser.io.subMsgHeadReq.bits.operator
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upSubMsgHeadInfo(1).length := upRecParser.io.subMsgHeadReq.bits.length
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upSubMsgHeadInfo(1).source := 1.U
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}
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}
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when( upRecParser.io.subMsgTailReq.fire ){
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when( isUpRecPing ){
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upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt
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} .otherwise{
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upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt
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}
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}
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//子报文下行发送
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val isDownSendPing = RegInit(false.B)
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val isUpSendPing = RegInit(false.B)
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downSendGen.io.subMsgHeadReq.valid :=
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( isDownSendPing & isDownSubMsgHeadValid(0) ) | (~isDownSendPing & isDownSubMsgHeadValid(1))
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downSendGen.io.subMsgHeadReq.bits := Mux( isDownSendPing, downSubMsgHeadInfo(0), downSubMsgHeadInfo(1) )
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downSendGen.io.subMsgTailReq.valid :=
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( isDownSendPing & isDownSubMsgTailValid(0) ) | ( ~isDownSendPing & isDownSubMsgTailValid(1))
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downSendGen.io.subMsgTailReq.bits := Mux( isDownSendPing, downSubMsgTailInfo(0), downSubMsgTailInfo(1) )
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when( downSendGen.io.subMsgHeadReq.fire ){ //ready
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when( isDownSendPing ){
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assert( isDownSubMsgHeadValid(0) )
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isDownSubMsgHeadValid(0) := false.B
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} .otherwise{
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assert( isDownSubMsgHeadValid(1) )
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isDownSubMsgHeadValid(1) := false.B
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}
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} .elsewhen( downRecParser.io.subMsgHeadReq.fire ){
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when( isDownRecPing ){
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assert( ~isDownSubMsgHeadValid(0) )
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isDownSubMsgHeadValid(0) := true.B
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} .otherwise{
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assert( ~isDownSubMsgHeadValid(1) )
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isDownSubMsgHeadValid(1) := true.B
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}
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}
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when( downSendGen.io.subMsgTailReq.fire ){
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when( isDownSendPing ){
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assert( isDownSubMsgTailValid(0) )
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isDownSubMsgTailValid(0) := false.B
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} .otherwise{
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assert( isDownSubMsgTailValid(1) )
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isDownSubMsgTailValid(1) := false.B
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}
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} .elsewhen( downRecParser.io.subMsgTailReq.fire ){
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when( isDownRecPing ){
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assert( ~isDownSubMsgTailValid(0) )
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isDownSubMsgTailValid(0) := true.B
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} .otherwise{
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assert( ~isDownSubMsgTailValid(1) )
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isDownSubMsgTailValid(1) := true.B
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}
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}
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when( downSendGen.io.subMsgTailReq.fire ){ //ready
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isDownSendPing := ~isDownSendPing
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} .elsewhen( downRecParser.io.subMsgTailReq.fire ){
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isDownRecPing := ~isDownRecPing
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}
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downRecFifo(0).io.deq <> downSendGen.io.data(0)
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downRecFifo(1).io.deq <> downSendGen.io.data(1)
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//子报文上行发送
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upSendGen.io.subMsgHeadReq.valid :=
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( isUpSendPing & isUpSubMsgHeadValid(0) ) |
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( ~isUpSendPing & isUpSubMsgHeadValid(1) )
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upSendGen.io.subMsgHeadReq.bits := Mux( isUpSendPing, upSubMsgHeadInfo(0), upSubMsgHeadInfo(1) )
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upSendGen.io.subMsgTailReq.valid :=
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( isUpSendPing & isUpSubMsgTailValid(0) ) |
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( ~isUpSendPing & isUpSubMsgTailValid(1) )
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upSendGen.io.subMsgTailReq.bits := Mux( isUpSendPing, upSubMsgTailInfo(0), upSubMsgTailInfo(1) )
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when( upSendGen.io.subMsgHeadReq.fire ){ //ready
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when( isUpSendPing ){
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assert( isUpSubMsgHeadValid(0) )
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isUpSubMsgHeadValid(0) := false.B
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} .otherwise{
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assert( isUpSubMsgHeadValid(1) )
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isUpSubMsgHeadValid(1) := false.B
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}
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}.elsewhen( upRecParser.io.subMsgHeadReq.fire ){
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when( isUpRecPing ){
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assert( ~isUpSubMsgHeadValid(0) )
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isUpSubMsgHeadValid(0) := true.B
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} .otherwise{
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assert( ~isUpSubMsgHeadValid(1) )
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isUpSubMsgHeadValid(1) := true.B
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}
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}
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when( upSendGen.io.subMsgTailReq.fire ){
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when( isUpSendPing ){
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assert( isUpSubMsgTailValid(0) )
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isUpSubMsgTailValid(0) := false.B
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} .otherwise{
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assert( isUpSubMsgTailValid(1) )
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isUpSubMsgTailValid(1) := false.B
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}
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} .elsewhen( upRecParser.io.subMsgTailReq.fire ){
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when( isUpRecPing ){
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assert( ~isUpSubMsgTailValid(0) )
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isUpSubMsgTailValid(0) := true.B
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} .otherwise{
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assert( ~isUpSubMsgTailValid(1) )
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isUpSubMsgTailValid(1) := true.B
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}
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}
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when( upSendGen.io.subMsgTailReq.fire ){ //ready
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isUpSendPing := ~isUpSendPing
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}.elsewhen( upRecParser.io.subMsgTailReq.fire ){
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isUpRecPing := ~isUpRecPing
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}
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upRecFifo(0).io.deq <> upSendGen.io.data(0)
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upRecFifo(1).io.deq <> upSendGen.io.data(1)
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}
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trait SlaveParserIndex{ this: SlaveParserBase =>
|
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//下行接收
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when( downRecParser.io.subMsgTailReq.fire ){
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when( isDownRecPing &
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downSubMsgHeadInfo(0).devIndex === 0.U &
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downSubMsgHeadInfo(0).style === 0.U &
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downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_INDEX
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){
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localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
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indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U)
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downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
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} .elsewhen( ~isDownRecPing &
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downSubMsgHeadInfo(1).devIndex === 0.U &
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downSubMsgHeadInfo(1).style === 0.U &
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downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_INDEX
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){ //pong
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localDevIndex := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
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indexOfRightDev := Mux(isLastDevice, 0.U, downRecParser.io.subMsgTailReq.bits.workCnt + 2.U)
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downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
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}
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}
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}
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trait SlaveParserRW{ this: SlaveParserBase =>
|
||
|
||
val isDownLgcWorked = RegInit(false.B)
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val isUpLgcWorked = RegInit(false.B)
|
||
|
||
//下行接收
|
||
when( downRecParser.io.subMsgTailReq.fire ){
|
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when( isDownRecPing ){
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//override
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||
when(
|
||
( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & isDownLgcWorked ) ) ) |
|
||
( ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||
) { //自身包//写操作或读写操作)
|
||
downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||
}
|
||
|
||
} .otherwise{ //pong
|
||
//override
|
||
when(
|
||
( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE ) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & isDownLgcWorked ) ) ) |
|
||
( ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||
) { //自身包//写操作或读写操作 )
|
||
downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
|
||
//写入 SM或寄存器空间
|
||
|
||
val addrw = RegInit(0.U(15.W))
|
||
val logicAddrwNext = Wire( UInt(30.W) )
|
||
val logicAddrw = RegNext(logicAddrwNext, 0.U(30.W))
|
||
|
||
val isWRReg = (addrw(14,11) === "b0000".U)
|
||
val isWRSM0 = (addrw(14,11) === "b0001".U)
|
||
val isWRSM2 = (addrw(14,11) === "b0011".U)
|
||
val isWRSM4 = (addrw(14,11) === "b0101".U)
|
||
val isWRSM6 = (addrw(14,11) === "b0111".U)
|
||
|
||
val downTransLenCnt = RegInit(0.U)
|
||
|
||
val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
|
||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(0).isSeqIndex & downSubMsgHeadInfo(0).devIndex === localDevIndex) || ( downSubMsgHeadInfo(0).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
|
||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgHeadInfo(1).isSeqIndex & downSubMsgHeadInfo(1).devIndex === localDevIndex) || ( downSubMsgHeadInfo(1).isLgcIndex & downTransLenCnt =/= 0.U) ) ) |
|
||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) |
|
||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||
)
|
||
|
||
|
||
val isDownLgcAddrwAcquireTrans = //是否触发地址转换
|
||
(downTransLenCnt === 0.U) & ( (0 until 16).map{ i =>
|
||
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)
|
||
}.reduce(_|_))
|
||
|
||
val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu
|
||
(0 until 16).map{ i =>
|
||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
|
||
sReg.ebmmu(i).pAddr
|
||
}
|
||
)
|
||
|
||
val acquireDownTransLen = Mux1H( //选择一个ebmmu
|
||
(0 until 16).map{ i =>
|
||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
|
||
sReg.ebmmu(i).length
|
||
}
|
||
)
|
||
|
||
when( isDownLgcAddrwAcquireTrans ){ //装填计数器
|
||
downTransLenCnt := acquireDownTransLen
|
||
} .elsewhen( downRecParser.io.data.fire & downTransLenCnt =/= 0.U){
|
||
downTransLenCnt := downTransLenCnt - 1.U
|
||
}
|
||
|
||
when( downRecParser.io.subMsgTailReq.fire ){
|
||
isDownLgcWorked := false.B
|
||
} .elsewhen( isDownLgcAddrwAcquireTrans ){
|
||
isDownLgcWorked := true.B
|
||
}
|
||
|
||
//组合逻辑
|
||
when( downRecParser.io.subMsgHeadReq.fire & (
|
||
(downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex
|
||
)){//组合逻辑
|
||
logicAddrwNext := Cat( downRecParser.io.subMsgHeadReq.bits.devIndex, downRecParser.io.subMsgHeadReq.bits.address )
|
||
} .elsewhen( downRecParser.io.data.fire & (
|
||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
|
||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
|
||
)){//组合逻辑
|
||
logicAddrwNext := logicAddrw + 1.U
|
||
} .otherwise{//组合逻辑
|
||
logicAddrwNext := logicAddrw
|
||
}
|
||
|
||
when(
|
||
( (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isSeqIndex & downRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex ) |
|
||
( downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
|
||
){ //常规寻址
|
||
when( downRecParser.io.subMsgHeadReq.fire ){ //子包头装填
|
||
addrw := downRecParser.io.subMsgHeadReq.bits.address
|
||
} .elsewhen( isWrite & downRecParser.io.data.fire ){
|
||
addrw := addrw + 1.U
|
||
}
|
||
} .elsewhen( isDownLgcAddrwAcquireTrans & (
|
||
( downRecParser.io.subMsgHeadReq.fire & (downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgHeadReq.bits.isLgcIndex ) |
|
||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
|
||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
|
||
)){
|
||
addrw := acquireDownPhyAddrw
|
||
} .elsewhen(
|
||
isWrite & downRecParser.io.data.fire & (
|
||
( isDownRecPing & ( (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(0).isLgcIndex ) |
|
||
( ~isDownRecPing & ( (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & downSubMsgHeadInfo(1).isLgcIndex )
|
||
) ){
|
||
assert(~isDownLgcAddrwAcquireTrans)
|
||
addrw := Mux( downTransLenCnt === 0.U, 0.U, addrw + 1.U )
|
||
}
|
||
|
||
io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire
|
||
io.lvds.dataw := downRecParser.io.data.bits
|
||
|
||
io.sram_w(0).enw := isWrite & isWRSM0 & downRecParser.io.data.fire
|
||
io.sram_w(0).addrw := addrw(10,0)
|
||
io.sram_w(0).dataw := downRecParser.io.data.bits
|
||
|
||
io.sram_w(1).enw := isWrite & isWRSM2 & downRecParser.io.data.fire
|
||
io.sram_w(1).addrw := addrw(10,0)
|
||
io.sram_w(1).dataw := downRecParser.io.data.bits
|
||
|
||
io.sram_w(2).enw := isWrite & isWRSM4 & downRecParser.io.data.fire
|
||
io.sram_w(2).addrw := addrw(10,0)
|
||
io.sram_w(2).dataw := downRecParser.io.data.bits
|
||
|
||
io.sram_w(3).enw := isWrite & isWRSM6 & downRecParser.io.data.fire
|
||
io.sram_w(3).addrw := addrw(10,0)
|
||
io.sram_w(3).dataw := downRecParser.io.data.bits
|
||
|
||
|
||
|
||
|
||
|
||
//上行接收
|
||
when( upRecParser.io.subMsgTailReq.fire ){
|
||
when( isUpRecPing ){
|
||
//override
|
||
when(
|
||
( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) || (upSubMsgHeadInfo(0).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||
( ( (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||
){ //自身包//读或读写
|
||
upSubMsgTailInfo(0).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||
}
|
||
} .otherwise{
|
||
//override
|
||
when(
|
||
( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD ) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) || (upSubMsgHeadInfo(1).isLgcIndex & isUpLgcWorked =/= 0.U ) ) ) |
|
||
( ( (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD) | (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) )
|
||
){ //自身包//读或读写 )
|
||
upSubMsgTailInfo(1).workCnt := upRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
|
||
|
||
|
||
val upTransLenCnt = RegInit(0.U)
|
||
|
||
|
||
val addrr = RegInit(0.U(15.W))
|
||
val logicAddrrNext = Wire( UInt(30.W) )
|
||
val logicAddrr = RegNext(logicAddrrNext, 0.U(30.W))
|
||
|
||
|
||
val isUpLgcAddrrAcquireTrans = //是否触发地址转换
|
||
(upTransLenCnt === 0.U) & ( (0 until 16).map{ i =>
|
||
sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)
|
||
}.reduce(_|_))
|
||
|
||
val acquireUpPhyAddrr = Mux1H( //选择一个ebmmu
|
||
(0 until 16).map{ i =>
|
||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
|
||
sReg.ebmmu(i).pAddr
|
||
}
|
||
)
|
||
|
||
val acquireUpTransLen = Mux1H( //选择一个ebmmu
|
||
(0 until 16).map{ i =>
|
||
(sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrrNext === sReg.ebmmu(i).lAddr)) ->
|
||
sReg.ebmmu(i).length
|
||
}
|
||
)
|
||
|
||
when( isUpLgcAddrrAcquireTrans & (
|
||
(upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
|
||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
|
||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
|
||
)){ //装填计数器
|
||
upTransLenCnt := acquireUpTransLen
|
||
} .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U ){
|
||
upTransLenCnt := upTransLenCnt - 1.U
|
||
}
|
||
|
||
when( upRecParser.io.subMsgTailReq.fire ){
|
||
isUpLgcWorked := false.B
|
||
} .elsewhen( isUpLgcAddrrAcquireTrans ){
|
||
isUpLgcWorked := true.B
|
||
}
|
||
|
||
//组合逻辑
|
||
when( upRecParser.io.subMsgHeadReq.fire & (
|
||
(upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex
|
||
)){//组合逻辑
|
||
logicAddrrNext := Cat( upRecParser.io.subMsgHeadReq.bits.devIndex, upRecParser.io.subMsgHeadReq.bits.address )
|
||
} .elsewhen( upRecParser.io.data.fire){
|
||
when(
|
||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(0).isLgcIndex ) |
|
||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgHeadInfo(1).isLgcIndex )
|
||
){//组合逻辑
|
||
logicAddrrNext := logicAddrr + 1.U
|
||
} .otherwise{
|
||
logicAddrrNext := 0.U
|
||
}
|
||
} .otherwise{//组合逻辑
|
||
logicAddrrNext := logicAddrr
|
||
}
|
||
|
||
|
||
val isRDReg = addrr(14,11) === "b0000".U
|
||
val isRDSM1 = addrr(14,11) === "b0010".U
|
||
val isRDSM3 = addrr(14,11) === "b0100".U
|
||
val isRDSM5 = addrr(14,11) === "b0110".U
|
||
val isRDSM7 = addrr(14,11) === "b1000".U
|
||
|
||
val isSeqRead =
|
||
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
|
||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) )) |
|
||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) )) |
|
||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
|
||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
|
||
)
|
||
) & ( (RegNext(upRecParser.io.stateCurr, STATE_IDLE) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
|
||
|
||
val isLgcRead =
|
||
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
|
||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
|
||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
|
||
)
|
||
) & ( RegNext(isUpLgcAddrrAcquireTrans, false.B) | upRecParser.io.data.fire )
|
||
|
||
val isLvdsEnR = isSeqRead | isLgcRead
|
||
|
||
|
||
|
||
when(
|
||
((upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgHeadReq.bits.isSeqIndex & upRecParser.io.subMsgHeadReq.bits.devIndex === localDevIndex)) |
|
||
( upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
|
||
){
|
||
when( upRecParser.io.subMsgHeadReq.fire){
|
||
addrr := upRecParser.io.subMsgHeadReq.bits.address
|
||
} .elsewhen(isLvdsEnR){
|
||
addrr := addrr + 1.U
|
||
}
|
||
} .elsewhen( isUpLgcAddrrAcquireTrans & (
|
||
(upRecParser.io.subMsgHeadReq.fire & (upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgHeadReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgHeadReq.bits.isLgcIndex) |
|
||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
|
||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
|
||
)){
|
||
addrr := acquireUpPhyAddrr
|
||
} .elsewhen( isLvdsEnR & (
|
||
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(0).isLgcIndex )) |
|
||
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( upSubMsgHeadInfo(1).isLgcIndex ))
|
||
)){
|
||
assert(~isUpLgcAddrrAcquireTrans)
|
||
addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
|
||
}
|
||
|
||
|
||
|
||
val upStreamData = Mux1H(Seq(
|
||
isRDReg -> io.lvds.datar,
|
||
isRDSM1 -> io.sram_r(0).datar,
|
||
isRDSM3 -> io.sram_r(1).datar,
|
||
isRDSM5 -> io.sram_r(2).datar,
|
||
isRDSM7 -> io.sram_r(3).datar,
|
||
))
|
||
|
||
|
||
when( isUpRecPing ){
|
||
upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
|
||
upRecFifo(0).io.enq.bits :=
|
||
Mux(
|
||
( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(0).isSeqIndex & upSubMsgHeadInfo(0).devIndex === localDevIndex) | (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
|
||
Mux( upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
|
||
upRecParser.io.data.bits )
|
||
)
|
||
upRecParser.io.data.ready := upRecFifo(0).io.enq.ready
|
||
|
||
upRecFifo(1).io.enq.valid := false.B
|
||
upRecFifo(1).io.enq.bits := 0.U
|
||
} .otherwise{
|
||
upRecFifo(0).io.enq.valid := false.B
|
||
upRecFifo(0).io.enq.bits := 0.U
|
||
|
||
upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
|
||
upRecFifo(1).io.enq.bits :=
|
||
Mux(
|
||
( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgHeadInfo(1).isSeqIndex & upSubMsgHeadInfo(1).devIndex === localDevIndex) | (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U)), upStreamData,
|
||
Mux( upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
|
||
upRecParser.io.data.bits
|
||
)
|
||
)
|
||
upRecParser.io.data.ready := upRecFifo(1).io.enq.ready
|
||
|
||
}
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
io.lvds.addrr := addrr(10,0)
|
||
io.lvds.addrw := addrw(10,0)
|
||
|
||
|
||
// assert( ~(isRead & isWrite) )
|
||
|
||
|
||
|
||
io.lvds.isEnR := isRDReg & isLvdsEnR
|
||
io.sram_r(0).enr := isRDSM1 & isLvdsEnR
|
||
io.sram_r(1).enr := isRDSM3 & isLvdsEnR
|
||
io.sram_r(2).enr := isRDSM5 & isLvdsEnR
|
||
io.sram_r(3).enr := isRDSM7 & isLvdsEnR
|
||
|
||
io.sram_r(0).addrr := addrr(10,0)
|
||
io.sram_r(1).addrr := addrr(10,0)
|
||
io.sram_r(2).addrr := addrr(10,0)
|
||
io.sram_r(3).addrr := addrr(10,0)
|
||
|
||
|
||
io.dSMenq(0) := io.sram_w(0).enw & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
|
||
io.uSMdeq(0) := isLvdsEnR & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U + 1.U) === addrr(10,0)
|
||
io.dSMenq(1) := io.sram_w(1).enw & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
|
||
io.uSMdeq(1) := isLvdsEnR & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U + 1.U) === addrr(10,0)
|
||
io.dSMenq(2) := io.sram_w(2).enw & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
|
||
io.uSMdeq(2) := isLvdsEnR & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U + 1.U) === addrr(10,0)
|
||
io.dSMenq(3) := io.sram_w(3).enw & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
|
||
io.uSMdeq(3) := isLvdsEnR & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U + 1.U) === addrr(10,0)
|
||
|
||
|
||
}
|
||
|
||
|
||
trait SlaveParserSync{ this: SlaveParserBase =>
|
||
val addr64_op1 = WireDefault( 0.U(64.W) )
|
||
val addr64_op2 = WireDefault( 0.U(64.W) )
|
||
def subOp2(x:UInt) = ~x + 1.U
|
||
val addr64_res = addr64_op1 + addr64_op2
|
||
|
||
val addrConflict = WireDefault(VecInit(Seq.fill(4){false.B}))
|
||
dontTouch(addrConflict)
|
||
assert( PopCount(addrConflict) <= 1.U )
|
||
|
||
|
||
//下行接收
|
||
when( downRecParser.io.subMsgTailReq.fire ){
|
||
when( isDownRecPing ){
|
||
//override
|
||
when( downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) { //同步包
|
||
downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||
}
|
||
|
||
} .otherwise{ //pong
|
||
//override
|
||
when( downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 )
|
||
downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U
|
||
}
|
||
}
|
||
}
|
||
|
||
|
||
|
||
val downTimeStamp = RegInit(0.U(64.W)) //下行本地时间戳寄存器
|
||
val upTimeStamp = RegInit(0.U(64.W)) //上行本地时间戳寄存器
|
||
val mstTimeStamp = RegInit(0.U(64.W)) //主站时间戳
|
||
val mstDeltaTimeStamp = RegInit(0.U(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
|
||
val slvDeltaTimeStamp = RegInit(0.U(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
|
||
|
||
val mstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主发从接时间差(中间变量)
|
||
val deltaMstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主差从差时间差(中间变量)
|
||
val deltaFinal = RegInit(0.U(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
|
||
|
||
// recoTimeStamp = io.timeStamp + deltaFinal
|
||
// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
|
||
// recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - slvDeltaTimeStamp ) >> 1
|
||
// recoTimeStamp = io.timeStamp + mstTimeStamp - downTimeStamp + (mstDeltaTimeStamp - (upTimeStamp - downTimeStamp)) >> 1
|
||
|
||
|
||
//更新下行本地时间戳寄存器
|
||
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){
|
||
downTimeStamp := io.cReg.timeStamp
|
||
}
|
||
|
||
//更新上行本地时间戳寄存器
|
||
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){
|
||
upTimeStamp := io.cReg.timeStamp
|
||
|
||
// slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp
|
||
addr64_op1 := io.cReg.timeStamp //组合逻辑
|
||
addr64_op2 := subOp2(downTimeStamp) //组合逻辑
|
||
addrConflict(0) := true.B //组合逻辑
|
||
slvDeltaTimeStamp := addr64_res //时序逻辑
|
||
}
|
||
|
||
//下行接收
|
||
val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
|
||
( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) |
|
||
( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
|
||
)
|
||
|
||
val syncCnt = RegInit(0.U(4.W))
|
||
|
||
when( downRecParser.io.rec.fire ){
|
||
when( isSync ){
|
||
syncCnt := syncCnt + 1.U
|
||
} .otherwise{
|
||
syncCnt := 0.U
|
||
}
|
||
}
|
||
|
||
|
||
when( isSync & downRecParser.io.rec.fire ){
|
||
when( syncCnt === 0.U ){
|
||
mstTimeStamp := Cat( mstTimeStamp(63, 8), downRecParser.io.data.bits )
|
||
} .elsewhen( syncCnt === 1.U ){
|
||
mstTimeStamp := Cat( mstTimeStamp(63,16), downRecParser.io.data.bits, mstTimeStamp(7,0) )
|
||
} .elsewhen( syncCnt === 2.U ){
|
||
mstTimeStamp := Cat( mstTimeStamp(63,24), downRecParser.io.data.bits, mstTimeStamp(15,0) )
|
||
} .elsewhen( syncCnt === 3.U ){
|
||
mstTimeStamp := Cat( mstTimeStamp(63,32), downRecParser.io.data.bits, mstTimeStamp(23,0) )
|
||
} .elsewhen( syncCnt === 4.U ){
|
||
mstTimeStamp := Cat( mstTimeStamp(63,40), downRecParser.io.data.bits, mstTimeStamp(31,0) )
|
||
} .elsewhen( syncCnt === 5.U ){
|
||
mstTimeStamp := Cat( mstTimeStamp(63,48), downRecParser.io.data.bits, mstTimeStamp(39,0) )
|
||
} .elsewhen( syncCnt === 6.U ){
|
||
mstTimeStamp := Cat( mstTimeStamp(63,56), downRecParser.io.data.bits, mstTimeStamp(47,0) )
|
||
} .elsewhen( syncCnt === 7.U ){
|
||
mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
|
||
} .elsewhen( syncCnt === 8.U ){
|
||
// mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
|
||
|
||
addr64_op1 := mstTimeStamp //组合逻辑
|
||
addr64_op2 := subOp2(downTimeStamp) //组合逻辑
|
||
addrConflict(1) := true.B //组合逻辑
|
||
mstSlvDeltaTimeStamp := addr64_res //时序逻辑
|
||
|
||
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits )
|
||
} .elsewhen( syncCnt === 9.U ){
|
||
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
|
||
} .elsewhen( syncCnt === 10.U ){
|
||
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,24), downRecParser.io.data.bits, mstDeltaTimeStamp(15,0) )
|
||
} .elsewhen( syncCnt === 11.U ){
|
||
mstDeltaTimeStamp := Cat( downRecParser.io.data.bits, mstDeltaTimeStamp(23, 0) )
|
||
} .otherwise{
|
||
assert(false.B, "Wrong Sync SubMsg!\n")
|
||
}
|
||
}
|
||
|
||
when( RegNext(isSync, false.B) & ~isSync ){
|
||
// deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
|
||
|
||
addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑
|
||
addr64_op2 := subOp2( Cat( Fill(32, slvDeltaTimeStamp(31)), slvDeltaTimeStamp) ) //组合逻辑
|
||
addrConflict(2) := true.B //组合逻辑
|
||
deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑
|
||
|
||
} .elsewhen( RegNext(RegNext(isSync, false.B), false.B) & ~RegNext(isSync, false.B) ){
|
||
// deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
|
||
addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑
|
||
addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑
|
||
addrConflict(3) := true.B //组合逻辑
|
||
deltaFinal := addr64_res //时序逻辑
|
||
}
|
||
|
||
|
||
}
|
||
|
||
trait SlaveParserProbe{ this: SlaveParserBase =>
|
||
|
||
val probeRecCnt = RegInit(0.U(9.W))
|
||
val isWatchDogOverflow = probeRecCnt.andR
|
||
|
||
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
|
||
isReadyToProbe := true.B
|
||
when( downSendGen.io.stateCurr =/= STATE_IDLE ){
|
||
printf("Error! downSendGen is busy while a Probe-Frame arrival!\n")
|
||
}
|
||
} .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
|
||
isReadyToProbe := false.B
|
||
} .elsewhen( isWatchDogOverflow ){
|
||
isReadyToProbe := false.B
|
||
}
|
||
|
||
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
|
||
isAckProbe := true.B
|
||
} .elsewhen( upSendGen.io.frameReq.fire & upSendGen.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行发送回复嗅探包
|
||
isAckProbe := false.B
|
||
}
|
||
|
||
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
|
||
isLastDevice := false.B
|
||
} .elsewhen( isWatchDogOverflow ){
|
||
isLastDevice := true.B
|
||
}
|
||
|
||
|
||
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
|
||
probeRecCnt := 0.U
|
||
} .elsewhen( isWatchDogOverflow ){
|
||
probeRecCnt := 0.U
|
||
} .elsewhen( isReadyToProbe ){
|
||
probeRecCnt := probeRecCnt + 1.U
|
||
}
|
||
|
||
|
||
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
|
||
indexOfRightDev := upRecParser.io.frameReq.bits.frameInfo
|
||
when( upRecParser.io.frameReq.bits.frameInfo =/= localDevIndex + 1.U ){ //索引不对
|
||
isDevOnRightModify := true.B
|
||
} .otherwise{
|
||
isDevOnRightModify := false.B
|
||
}
|
||
}
|
||
|
||
|
||
|
||
|
||
|
||
|
||
io.upOut <> Queue( upSendGen.io.send, 4, true, false )
|
||
io.downIn <> downRecParser.io.rec
|
||
|
||
io.downOut <> Queue( downSendGen.io.send, 4, true, false )
|
||
io.upIn <> upRecParser.io.rec
|
||
|
||
io.isLoop := isLastDevice & ~isReadyToProbe
|
||
|
||
}
|
||
|
||
class SlaveParser extends SlaveParserBase
|
||
with SlaveParserIndex
|
||
with SlaveParserRW
|
||
with SlaveParserSync
|
||
with SlaveParserProbe{
|
||
io.intHWTrig(0) := downRecParser.io.isError
|
||
io.intHWTrig(1) := upRecParser.io.isError
|
||
|
||
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
|
||
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
|
||
|
||
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
|
||
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
|
||
|
||
io.downRecStat := downRecParser.io.stat
|
||
io.upRecStat := upRecParser.io.stat
|
||
}
|
||
|
||
|
||
|
||
|