456 lines
11 KiB
Scala
456 lines
11 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class FSMC_Port_Bundle extends Bundle{
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val ADIn = Input(UInt(16.W))
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val ADOut = Output(UInt(16.W))
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val ADOEn = Output(Bool())
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val csn = Input(Bool())
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val rdn = Input(Bool())
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val wrn = Input(Bool())
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val advn = Input(Bool())
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}
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class BackBoardMstIO extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val reset_calib = Input(Bool())
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val oser_pclk = Input(Bool()) //10M
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val oser_fclk = Input(Bool()) //50M
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val ides_pclk = Input(Bool()) //100M
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val ides_fclk = Input(Bool()) //400M
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val interrupt = Output(Bool())
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}
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class BackBoardMstBase extends Module{ //10M
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val io: BackBoardMstIO = IO(new BackBoardMstIO)
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val lvdsMst = Module(new Lvds_Bus_Master)
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val mirrorDown = Module(new MirrorSRAMDown())
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val mirrorUp = Module(new MirrorSRAMUp())
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val statusCDRErr = RegInit( false.B )
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val statusCRCErr = RegInit( false.B )
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val statusLinkErr = RegInit( false.B )
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val statusSynch = RegInit( false.B )
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val statusInit = RegInit( false.B )
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val ctrlTransmit = RegInit( false.B )
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val ctrlCDRErr = RegInit( false.B )
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val ctrlCRCErr = RegInit( false.B )
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val ctrlLinkErr = RegInit( false.B )
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val ctrlSynch = RegInit( false.B )
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val ctrlInit = RegInit( false.B )
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val slvNum = RegInit(0.U(6.W))
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val slvOffLine = RegInit(0.U(6.W))
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val linkNum = RegInit(0.U(7.W))
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val testReg = RegInit("haa55".U(16.W))
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val interrupt = RegInit(false.B); io.interrupt := interrupt
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lvdsMst.io.rst_n := ~reset.asBool
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lvdsMst.io.reset_calib := io.reset_calib
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lvdsMst.io.oser_pclk := io.oser_pclk
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lvdsMst.io.oser_fclk := io.oser_fclk
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lvdsMst.io.ides_pclk := io.ides_pclk
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lvdsMst.io.ides_fclk := io.ides_fclk
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io.lvds_down_dout := lvdsMst.io.lvds_down_dout
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lvdsMst.io.lvds_up_din := io.lvds_up_din
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mirrorDown.io.clockr := io.oser_pclk.asBool
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mirrorDown.io.clockw := io.ides_pclk.asBool //100M
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mirrorUp.io.clockw := io.oser_pclk.asBool
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mirrorUp.io.clockr := io.ides_pclk.asBool //100M
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when(interrupt === true.B){
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interrupt := false.B
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}
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}
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trait BackBoardMstFSMC{ this: BackBoardMstBase =>
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val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
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val wrRegAddr = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) } //100M
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val wrRegData = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) } //100M
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withClockAndReset( io.ides_pclk.asClock, reset ){//100M
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val fsmcCSSync = ShiftRegisters( ~io.FSMC.csn, 3, false.B, true.B )
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val fsmcRDSync = ShiftRegisters( ~io.FSMC.rdn, 3, false.B, true.B )
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val fsmcWRSync = ShiftRegisters( ~io.FSMC.wrn, 3, false.B, true.B )
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val fsmcADVSync = ShiftRegisters( ~io.FSMC.advn, 3, false.B, true.B )
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io.FSMC.ADOEn := fsmcRDSync(0) & fsmcCSSync(0) & ~fsmcADVSync(0)
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val latchAddr = RegEnable( io.FSMC.ADIn, (~fsmcADVSync(1) & fsmcADVSync(0) & fsmcCSSync(0)) | (fsmcADVSync(0) & ~fsmcCSSync(1) & fsmcCSSync(0)) )
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val isAccessSRAM = ~latchAddr.extract(10)
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val isAccessReg = latchAddr.extract(10)
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val activeAddr = latchAddr(9,0)
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val regOut = Wire(UInt(16.W))
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mirrorDown.io.enw := isAccessSRAM & fsmcCSSync(0) & fsmcWRSync(0)
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mirrorDown.io.addrw := activeAddr
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mirrorDown.io.dataw := io.FSMC.ADIn
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mirrorUp.io.enr := isAccessSRAM & fsmcCSSync(0) & fsmcRDSync(0)
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mirrorUp.io.addrr := activeAddr
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io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
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regOut := Mux1H(Seq(
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( activeAddr === 0.U) ->
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Cat(
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statusCDRErr ,
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statusCRCErr ,
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statusLinkErr,
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statusSynch ,
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statusInit
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),
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( activeAddr === 1.U) ->
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Cat(
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ctrlTransmit,
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0.U(1.W),
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0.U(1.W),
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0.U(1.W),
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ctrlSynch,
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ctrlInit
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),
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( activeAddr === 2.U) -> slvNum,
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( activeAddr === 3.U) -> slvOffLine,
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( activeAddr === 4.U) -> testReg,
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( activeAddr === 5.U) -> linkNum,
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))
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when( isAccessReg & fsmcCSSync(0) & ~fsmcWRSync(1) & fsmcWRSync(0) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
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isRegRefleshFlip := ~isRegRefleshFlip
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wrRegAddr := activeAddr
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wrRegData := io.FSMC.ADIn
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}
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}
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//10M
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val isChkRegReflesh = RegInit(false.B)
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when( isChkRegReflesh =/= isRegRefleshFlip ){
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isChkRegReflesh := ~isChkRegReflesh
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when( wrRegAddr === 0.U ){
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when( wrRegData.extract(4) ){
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statusCDRErr := false.B
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}
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when( wrRegData.extract(3) ){
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statusCRCErr := false.B
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}
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when( wrRegData.extract(2) ){
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statusLinkErr := false.B
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}
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}
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when( wrRegAddr === 1.U ){
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ctrlTransmit := wrRegData.extract(5)
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ctrlSynch := wrRegData.extract(1)
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when( wrRegData.extract(0) ){
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ctrlInit := true.B
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statusSynch := false.B
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statusInit := false.B
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}
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}
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when( wrRegAddr === 4.U ){
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testReg := wrRegData
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}
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}
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}
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trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
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io.FSMC.ADOut := DontCare
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io.FSMC.ADOEn := DontCare
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val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
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when( powerUpCnt === 500.U ){
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ctrlInit := true.B
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}
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val ( _, isTransmitTimeout ) = Counter(Range( 0,520), statusInit, false.B)
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when(isTransmitTimeout){
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ctrlTransmit := true.B
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}
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mirrorDown.io.enw := true.B
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mirrorDown.io.addrw := powerUpCnt
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mirrorDown.io.dataw := "h5555".U
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mirrorUp.io.enr := false.B
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mirrorUp.io.addrr := 0.U
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}
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abstract class BackBoardMstLVDSBase extends BackBoardMstBase
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with BackBoardMstFSMC
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// with BackBoardMstSim
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{
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val frame_info_update_en = RegInit(false.B)
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val slave_type_num = RegInit(0.U(8.W))
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val slave_data_length = RegInit(0.U(8.W))
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val tx_start = RegInit(false.B)
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lvdsMst.io.frame_info_update_en := frame_info_update_en
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lvdsMst.io.slave_type_num := slave_type_num
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lvdsMst.io.slave_data_length := slave_data_length
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lvdsMst.io.tx_start := tx_start
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val stateCur = RegInit(15.U(4.W))
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}
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trait BackBoardMstLVDSInit{ this: BackBoardMstLVDSBase =>
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val isInitStart = ~RegNext(ctrlInit, false.B) & ctrlInit
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val timeoutCnt = Reg(UInt(13.W))
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when(ctrlInit){
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when( isInitStart ){
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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slave_data_length := 0.U
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tx_start := false.B
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} .elsewhen( stateCur === 0.U ){
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stateCur := 1.U
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frame_info_update_en := true.B
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slave_type_num := Cat( "b00".U(2.W), slvNum )
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slave_data_length := ((8/8)*32-1).U
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tx_start := false.B
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} .elsewhen( stateCur === 1.U ){ // tx start
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stateCur := 2.U
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timeoutCnt := 0.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 2.U ){
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tx_start := false.B
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timeoutCnt := timeoutCnt + 1.U
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when( lvdsMst.io.slave_link_num_valid ){
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linkNum := lvdsMst.io.slave_link_num
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stateCur := 3.U
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statusInit := true.B
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ctrlInit := false.B
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interrupt := true.B
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}
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when( timeoutCnt === 6000.U ){
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linkNum := 0.U
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stateCur := 3.U
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statusInit := true.B
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ctrlInit := false.B
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interrupt := true.B
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}
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} .elsewhen( stateCur === 3.U ){
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}
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}
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}
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trait BackBoardMstLVDSSync{ this: BackBoardMstLVDSBase =>
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val isSyncStart = ~RegNext( ctrlSynch, false.B) & ctrlSynch
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when( ctrlSynch ){
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when( isSyncStart ){
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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slave_data_length := 0.U
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tx_start := false.B
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}.elsewhen( stateCur === 0.U ){
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stateCur := 1.U
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frame_info_update_en := true.B
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slave_type_num := Cat( "b01".U(2.W), slvNum )
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slave_data_length := ((8/8)*32-1).U
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tx_start := false.B
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} .elsewhen( stateCur === 1.U ){ // tx start
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stateCur := 2.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 2.U ){
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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stateCur := 3.U
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statusSynch := true.B
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ctrlSynch := false.B
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interrupt := true.B
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}
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} .elsewhen( stateCur === 3.U ){
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}
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.otherwise{
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}
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}
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}
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trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
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val isTransStart = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)
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when(ctrlTransmit){
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when( isTransStart ){ //reset
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stateCur := 0.U
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frame_info_update_en := false.B
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slave_type_num := 0.U
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slave_data_length := 0.U
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tx_start := false.B
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} .elsewhen( stateCur === 0.U ){ //setting
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stateCur := 1.U
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frame_info_update_en := true.B
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slave_type_num := Cat( "b10".U(2.W), slvNum )
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slave_data_length := ((8/8)*32-1).U
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tx_start := false.B
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} .elsewhen( stateCur === 1.U ){ // tx start
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stateCur := 2.U
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frame_info_update_en := false.B
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tx_start := true.B
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} .elsewhen( stateCur === 2.U ){ //waiting for busy drop
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tx_start := false.B
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when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
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stateCur := 3.U
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}
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} .elsewhen( stateCur === 3.U ){
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stateCur := 4.U
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ctrlTransmit := false.B
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interrupt := true.B
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} .otherwise{
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}
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}
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val addrr = RegInit(0.U(11.W))
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val addrw = RegInit(0.U(11.W))
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when( isTransStart ){
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addrw := 0.U
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} .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){
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assert( (stateCur === 2.U) || (stateCur === 3.U) )
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addrw := addrw + 1.U
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}
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when( isTransStart ){
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addrr := 0.U
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} .elsewhen( lvdsMst.io.tx_data_ready & ctrlTransmit){
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addrr := addrr + 1.U
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}
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mirrorDown.io.enr := (stateCur === 1.U || stateCur === 2.U) & ctrlTransmit
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lvdsMst.io.tx_data_in := mirrorDown.io.datar
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mirrorDown.io.addrr := addrr
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mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ctrlTransmit
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mirrorUp.io.dataw := lvdsMst.io.rx_data_out
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mirrorUp.io.addrw := addrw
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}
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trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
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when( lvdsMst.io.closed_loop_err ){
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slvOffLine := lvdsMst.io.link_err_location(5,0)
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statusLinkErr := true.B
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interrupt := true.B
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}
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when( lvdsMst.io.upstream_cdr_err ){
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statusCDRErr := true.B
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interrupt := true.B
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}
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when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
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statusCRCErr := true.B
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interrupt := true.B
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}
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}
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class BackBoardMst extends BackBoardMstLVDSBase
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with BackBoardMstLVDSInit
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with BackBoardMstLVDSSync
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with BackBoardMstLVDSTransmit
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with BackBoardMstLVDSError
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