RuigeLee
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ff7aba38ad
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拆分CDRIn为采样部分和axis部分；调整层次结构，仅将cdrInSample放在顶层；放置3组CDRInSample，使用寄存器选择
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2025-09-06 11:07:41 +08:00 |
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RuigeLee
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d5523eaa46
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Merge branch 'feature/clk3_shift_allow' into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# tb/shinTest/ShinTopSpiTb.v
# tb/shinTest/gen_pkt.py
# tb/shinTest/testcase/base.py
# tb/shinTest/testcase/environment.py
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2025-09-05 16:01:52 +08:00 |
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RuigeLee
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7b3b4c010d
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8B10B正负相写反
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2025-09-05 15:39:17 +08:00 |
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RuigeLee
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e9bc1d1e18
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cdrin的preamble连续监控10个cycle
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2025-09-05 15:09:52 +08:00 |
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RuigeLee
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adb1d9c1c8
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4b5b 8b10b接线完成
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2025-09-05 12:55:32 +08:00 |
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RuigeLee
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26344d60cd
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写完编解码模块
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2025-09-05 11:11:01 +08:00 |
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RuigeLee
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f609945a6a
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8b10b编码完成
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2025-09-05 09:35:29 +08:00 |
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RuigeLee
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0b7bd505ba
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b5b6编码表
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2025-09-04 16:25:54 +08:00 |
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RuigeLee
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cbd52792a5
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所有寄存器均复位
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2025-09-02 16:22:27 +08:00 |
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Ruige Lee
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a21d6eaf54
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确认波形
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2025-09-02 11:10:05 +08:00 |
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Ruige Lee
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706b9f17e5
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FPGA测试通过
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2025-08-27 17:06:31 +08:00 |
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Ruige Lee
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58ad17ce79
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修复
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2025-08-27 16:27:00 +08:00 |
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Ruige Lee
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bdabf08108
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Merge branch 'mp_eb_dev' into feature/clk3_shift_allow
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
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2025-08-27 14:59:39 +08:00 |
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Ruige Lee
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6f1101f6dc
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改异步复位，增加flush接口，删除其他工程代码以编译通过
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2025-08-25 19:16:27 +08:00 |
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Ruige Lee
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7dd8458f96
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允许正负3个cycle偏移
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2025-08-25 17:32:21 +08:00 |
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Ruige Lee
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0a0a7a7712
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修正解锁条件
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2025-08-22 14:24:41 +08:00 |
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Ruige Lee
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06996d6945
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锁定后允许在正负3相位之间校准
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2025-08-21 18:57:28 +08:00 |
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Ruige Lee
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6d8edfd6ce
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锁定后，每16个cycle ，或许有bug
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2025-08-20 19:08:51 +08:00 |
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Ruige Lee
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0291d445ca
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Revert "cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁"
This reverts commit d7146a786b.
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2025-08-20 15:40:25 +08:00 |
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Ruige Lee
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d7146a786b
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cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁
需要配平fifo，覆盖每个长度端，长度边缘，解锁在crc位置，不同preamble长度
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2025-08-19 17:04:58 +08:00 |
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Ruige Lee
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f3916df37b
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弃用高频率采样CDR的例化
Merge branch 'mp_eb_dev_多采样全表决' into mp_eb_dev
* mp_eb_dev_多采样全表决:
调整解锁条件为10个连续0
增加一个锁定可以暂时解决发送失败问题
滤波 表决 鉴相同时存在
enhance 要求先跨时钟，再进行后续表决
Revert "16相位改8相位"
16相位改8相位
bug: 16相位补充相 欠了一相
Revert "改6相位，从一个pll出，测试"
Revert "尝试3相位"
尝试3相位
改6相位，从一个pll出，测试
拉出测试IO
Revert "4多相位效果明显更好"
4多相位效果明显更好
16相位操作还是卡
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
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2025-08-19 10:00:25 +08:00 |
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Ruige Lee
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2fb450673f
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调整解锁条件为10个连续0
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2025-08-18 17:39:32 +08:00 |
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Ruige Lee
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2afd3f722a
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增加一个锁定可以暂时解决发送失败问题
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2025-08-18 16:20:50 +08:00 |
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Ruige Lee
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11bbf14226
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滤波 表决 鉴相同时存在
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2025-08-15 17:18:45 +08:00 |
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Ruige Lee
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45d2d223c1
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enhance 要求先跨时钟，再进行后续表决
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2025-08-15 15:28:28 +08:00 |
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Ruige Lee
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62684bd665
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Revert "16相位改8相位"
This reverts commit 2da45138db.
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2025-08-15 10:45:44 +08:00 |
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Ruige Lee
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2da45138db
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16相位改8相位
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2025-08-15 10:45:10 +08:00 |
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Ruige Lee
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fc917054ed
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bug: 16相位补充相 欠了一相
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2025-08-14 19:23:56 +08:00 |
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Ruige Lee
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573a1ad45f
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bug:滤波需要顺序打拍，防止边界上跳变
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2025-08-14 19:15:09 +08:00 |
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Ruige Lee
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035109bee1
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Revert "改6相位，从一个pll出，测试"
This reverts commit 495a238a26.
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2025-08-13 17:54:50 +08:00 |
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Ruige Lee
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4955b7a278
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Revert "尝试3相位"
This reverts commit c6aa7416fc.
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2025-08-13 17:54:39 +08:00 |
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Ruige Lee
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c6aa7416fc
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尝试3相位
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2025-08-13 10:52:49 +08:00 |
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Ruige Lee
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495a238a26
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改6相位，从一个pll出，测试
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2025-08-13 10:00:11 +08:00 |
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Ruige Lee
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cb2c4f46e5
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拉出测试IO
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2025-08-12 17:48:35 +08:00 |
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Ruige Lee
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107895f6e0
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Revert "4多相位效果明显更好"
This reverts commit 7338314c17.
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2025-08-12 09:55:43 +08:00 |
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Ruige Lee
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7338314c17
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4多相位效果明显更好
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2025-08-11 19:33:56 +08:00 |
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Ruige Lee
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b0b221e8b0
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16相位操作还是卡
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2025-08-11 18:13:58 +08:00 |
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Ruige Lee
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1cb0cee966
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should >= 3
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2025-08-11 10:07:54 +08:00 |
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Ruige Lee
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a31b08dcda
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Merge branch 'mp_eb_dev' of github.com:whutddk/RISCV-MAC-SWICH into mp_eb_dev
# Conflicts:
# src/main/scala/backBoard/ebus/CDROut.scala
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2025-08-11 10:07:18 +08:00 |
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Ruige Lee
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cae503f4c2
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preamble应该大于3
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2025-08-11 10:05:49 +08:00 |
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RuigeLee
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424e07a076
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增加5选3多数表决滤波
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2025-08-09 22:22:19 +08:00 |
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|
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1ce3840567
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PRE_NUM改为8后，功能正常
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2025-08-08 22:42:21 +08:00 |
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Ruige Lee
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dc4539124c
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可调preamble长度
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2025-08-07 17:39:11 +08:00 |
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Ruige Lee
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8c09a6c4aa
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写死16相位
Merge branch 'mp_eb_dev' into feature/multiPhaseCDRIn
# Conflicts:
# src/main/scala/backBoard/ebus/CDRIn.scala
# src/main/scala/backBoard/shin/ShinTop.scala
# tb/shinTest/ShinTopSpiTb.v
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2025-08-05 16:49:41 +08:00 |
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|
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656986a8ab
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:Merge branch 'feature_shintop' into eb_dev
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2025-07-30 23:14:37 +08:00 |
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Ruige Lee
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8ba8ff0e9e
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**抹除**加密特性
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2025-07-30 15:36:18 +08:00 |
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Ruige Lee
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302893c3e7
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加入CDR的滤波，并修改测试led
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2025-07-28 14:31:45 +08:00 |
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Ruige Lee
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9f88d26ba1
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多相位时钟可以使用
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2025-07-22 11:49:33 +08:00 |
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Ruige Lee
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7c632c8c1b
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编译通过
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2025-07-22 09:35:06 +08:00 |
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Ruige Lee
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bf8fce2671
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需要考虑多项位时钟是按同步时钟还是异步时钟处理
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2025-07-17 17:47:59 +08:00 |
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