RuigeLee
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589fc528a0
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compile pass
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2023-08-20 15:50:11 +08:00 |
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Ruige Lee
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f3a44f0b31
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slv
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2023-08-18 12:10:47 +00:00 |
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RuigeLee
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6fa2ef5f6e
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porta
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2023-08-16 22:25:30 +08:00 |
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Ruige Lee
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bbd0f0b887
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sync
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2023-08-16 06:12:49 +00:00 |
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Ruige Lee
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6c2f0b02f8
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FSMC
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2023-08-15 08:42:56 +00:00 |
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Ruige Lee
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939fa22be5
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wrapper of mst and slv
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2023-08-15 02:59:10 +00:00 |
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RuigeLee
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3211e21e11
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wrapper
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2023-08-14 22:46:50 +08:00 |
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RuigeLee
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1c7a226a70
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add function demo
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2023-08-09 14:43:24 +08:00 |
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RuigeLee
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68e0a6a055
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test pass
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2023-08-07 11:40:14 +08:00 |
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RuigeLee
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a041c7732a
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over sample in spi
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2023-08-07 10:15:56 +08:00 |
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RuigeLee
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d09aff40f2
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timing close
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2023-08-02 15:17:16 +08:00 |
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RuigeLee
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5d43600680
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fpga sync
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2023-08-01 15:50:53 +08:00 |
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RuigeLee
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35e6fcdb52
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mst test pass
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2023-08-01 14:44:05 +08:00 |
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RuigeLee
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24800cce9d
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spi compile pass
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2023-07-31 22:56:09 +08:00 |
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RuigeLee
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3aa4ca17d4
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all test pass
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2023-07-28 20:42:35 +08:00 |
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RuigeLee
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2048a4d286
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first test
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2023-07-28 15:38:46 +08:00 |
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Ruige
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85fe9175e6
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backplaneslv compile pass
Signed-off-by: Ruige <295054118@whut.edu.cn>
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2023-07-25 21:05:43 +08:00 |
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RuigeLee
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b1fd2db2e0
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backboard
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2023-07-24 19:31:32 +08:00 |
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RuigeLee
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440cefb02a
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we use async reset for different clock now
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2023-07-24 19:31:20 +08:00 |
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RuigeLee
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21f8547273
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ethreg Test pass
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2023-07-21 16:38:02 +08:00 |
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RuigeLee
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0b48e2cd2b
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compile pass
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2023-07-20 14:58:59 +08:00 |
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RuigeLee
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fa748b7de9
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Revert "create register node"
This reverts commit e558356a22.
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2023-07-20 10:35:56 +08:00 |
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RuigeLee
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e558356a22
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create register node
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2023-07-20 10:01:59 +08:00 |
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RuigeLee
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e3e1f6b6cb
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a new top for fpga; port mac-master to mem
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2023-07-17 21:41:34 +08:00 |
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RuigeLee
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25584bf6f5
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successfully interger in rocketchip
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2023-07-13 17:38:01 +08:00 |
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RuigeLee
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63be80135c
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tl to axi in single device
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2023-07-12 17:24:42 +08:00 |
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RuigeLee
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242765f106
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add trait
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2023-07-11 23:05:44 +08:00 |
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RuigeLee
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8b2121959e
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中断节点化
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2023-07-11 22:02:41 +08:00 |
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RuigeLee
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2d720b7c8d
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remove istilelink parameter
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2023-07-11 17:45:32 +08:00 |
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RuigeLee
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44048ea7d9
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remove all wishbone
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2023-07-11 17:38:18 +08:00 |
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RuigeLee
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3037d31028
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move tlsram to chisel
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2023-07-11 00:00:26 +08:00 |
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RuigeLee
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67f93bb464
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强拆wbmst，删除了burst特性，待功能测试通过后重做
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2023-07-07 21:43:06 +08:00 |
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RuigeLee
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9322f63bc5
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跨时钟域有严重设计缺陷
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2023-07-06 22:11:49 +08:00 |
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RuigeLee
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78a2f4ba47
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ready to test tilelink slv
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2023-07-04 23:36:34 +08:00 |
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RuigeLee
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5bd8b261bf
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compile tilelink
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2023-07-04 17:37:41 +08:00 |
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RuigeLee
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01853cecd1
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parameter, switch of diff slv bus
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2023-07-04 15:40:51 +08:00 |
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RuigeLee
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6efd11322b
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io merge
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2023-07-04 14:26:24 +08:00 |
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RuigeLee
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3886583b2a
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bug fixed
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2023-07-04 13:07:33 +08:00 |
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RuigeLee
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fd9bebe897
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compile and realign pass
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2023-07-04 10:00:08 +08:00 |
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RuigeLee
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0303ca21fb
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top layer and some bugs fixed
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2023-07-03 23:51:01 +08:00 |
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RuigeLee
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38bcf0dcf0
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tilelink should not add here
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2023-07-03 16:25:41 +08:00 |
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RuigeLee
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c65edfe4ae
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merge wb into tilelink files
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2023-06-30 20:21:03 +08:00 |
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RuigeLee
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374c6ecde0
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this is the last equal commit
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2023-06-30 16:14:58 +08:00 |
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RuigeLee
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d4ed6f39a0
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opt
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2023-06-30 16:00:02 +08:00 |
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RuigeLee
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546fea5903
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opt
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2023-06-30 14:46:23 +08:00 |
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RuigeLee
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cecf3caddc
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opt
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2023-06-29 23:28:05 +08:00 |
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RuigeLee
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59a2f2e054
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opt
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2023-06-29 21:14:51 +08:00 |
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RuigeLee
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61e36c59d8
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wishbone test pass
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2023-06-29 18:29:54 +08:00 |
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RuigeLee
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7aee6496f9
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wishbone almost
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2023-06-28 23:43:03 +08:00 |
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RuigeLee
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9e3786785c
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macregister
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2023-06-26 21:55:20 +08:00 |
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